coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Macros
pci_def.h File Reference

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Macros

#define PCI_VENDOR_ID   0x00 /* 16 bits */
 
#define PCI_DEVICE_ID   0x02 /* 16 bits */
 
#define PCI_COMMAND   0x04 /* 16 bits */
 
#define PCI_COMMAND_IO   0x1 /* Enable response in I/O space */
 
#define PCI_COMMAND_MEMORY   0x2 /* Enable response in Memory space */
 
#define PCI_COMMAND_MASTER   0x4 /* Enable bus mastering */
 
#define PCI_COMMAND_SPECIAL   0x8 /* Enable response to special cycles */
 
#define PCI_COMMAND_INVALIDATE   0x10 /* Use memory write and invalidate */
 
#define PCI_COMMAND_VGA_PALETTE   0x20 /* Enable palette snooping */
 
#define PCI_COMMAND_PARITY   0x40 /* Enable parity checking */
 
#define PCI_COMMAND_WAIT   0x80 /* Enable address/data stepping */
 
#define PCI_COMMAND_SERR   0x100 /* Enable SERR */
 
#define PCI_COMMAND_FAST_BACK   0x200 /* Enable back-to-back writes */
 
#define PCI_COMMAND_INT_DISABLE   0x400 /* Interrupt disable */
 
#define PCI_STATUS   0x06 /* 16 bits */
 
#define PCI_STATUS_CAP_LIST   0x10 /* Support Capability List */
 
#define PCI_STATUS_66MHZ   0x20 /* Support 66 Mhz PCI 2.1 bus */
 
#define PCI_STATUS_UDF   0x40
 
#define PCI_STATUS_FAST_BACK   0x80 /* Accept fast-back to back */
 
#define PCI_STATUS_PARITY   0x100 /* Detected parity error */
 
#define PCI_STATUS_DEVSEL_MASK   0x600 /* DEVSEL timing */
 
#define PCI_STATUS_DEVSEL_FAST   0x000
 
#define PCI_STATUS_DEVSEL_MEDIUM   0x200
 
#define PCI_STATUS_DEVSEL_SLOW   0x400
 
#define PCI_STATUS_SIG_TARGET_ABORT   0x800 /* Set on target abort */
 
#define PCI_STATUS_REC_TARGET_ABORT   0x1000 /* Master ack of " */
 
#define PCI_STATUS_REC_MASTER_ABORT   0x2000 /* Set on master abort */
 
#define PCI_STATUS_SIG_SYSTEM_ERROR   0x4000 /* Set when we drive SERR */
 
#define PCI_STATUS_DETECTED_PARITY   0x8000 /* Set on parity error */
 
#define PCI_CLASS_REVISION
 
#define PCI_REVISION_ID   0x08 /* Revision ID */
 
#define PCI_CLASS_PROG   0x09 /* Reg. Level Programming Interface */
 
#define PCI_CLASS_DEVICE   0x0a /* Device class */
 
#define PCI_CACHE_LINE_SIZE   0x0c /* 8 bits */
 
#define PCI_LATENCY_TIMER   0x0d /* 8 bits */
 
#define PCI_HEADER_TYPE   0x0e /* 8 bits */
 
#define PCI_HEADER_TYPE_NORMAL   0
 
#define PCI_HEADER_TYPE_BRIDGE   1
 
#define PCI_HEADER_TYPE_CARDBUS   2
 
#define PCI_BIST   0x0f /* 8 bits */
 
#define PCI_BIST_CODE_MASK   0x0f /* Return result */
 
#define PCI_BIST_START   0x40 /* 1 to start BIST, 2 secs or less */
 
#define PCI_BIST_CAPABLE   0x80 /* 1 if BIST capable */
 
#define PCI_BASE_ADDRESS_0   0x10 /* 32 bits */
 
#define PCI_BASE_ADDRESS_1   0x14 /* 32 bits [htype 0,1 only] */
 
#define PCI_BASE_ADDRESS_2   0x18 /* 32 bits [htype 0 only] */
 
#define PCI_BASE_ADDRESS_3   0x1c /* 32 bits */
 
#define PCI_BASE_ADDRESS_4   0x20 /* 32 bits */
 
#define PCI_BASE_ADDRESS_5   0x24 /* 32 bits */
 
#define PCI_BASE_ADDRESS_SPACE   0x01 /* 0 = memory, 1 = I/O */
 
#define PCI_BASE_ADDRESS_SPACE_IO   0x01
 
#define PCI_BASE_ADDRESS_SPACE_MEMORY   0x00
 
#define PCI_BASE_ADDRESS_MEM_LIMIT_MASK   0x06
 
#define PCI_BASE_ADDRESS_MEM_LIMIT_32   0x00 /* 32 bit address */
 
#define PCI_BASE_ADDRESS_MEM_LIMIT_1M   0x02 /* Below 1M [obsolete] */
 
#define PCI_BASE_ADDRESS_MEM_LIMIT_64   0x04 /* 64 bit address */
 
#define PCI_BASE_ADDRESS_MEM_PREFETCH   0x08 /* prefetchable? */
 
#define PCI_BASE_ADDRESS_MEM_ATTR_MASK   0x0f
 
#define PCI_BASE_ADDRESS_IO_ATTR_MASK   0x03
 
#define PCI_CARDBUS_CIS   0x28
 
#define PCI_SUBSYSTEM_VENDOR_ID   0x2c
 
#define PCI_SUBSYSTEM_ID   0x2e
 
#define PCI_ROM_ADDRESS   0x30
 
#define PCI_ROM_ADDRESS_ENABLE   0x01
 
#define PCI_ROM_ADDRESS_MASK   (~0x7ffUL)
 
#define PCI_CAPABILITY_LIST   0x34
 
#define PCI_INTERRUPT_LINE   0x3c /* 8 bits */
 
#define PCI_INTERRUPT_PIN   0x3d /* 8 bits */
 
#define PCI_MIN_GNT   0x3e /* 8 bits */
 
#define PCI_MAX_LAT   0x3f /* 8 bits */
 
#define PCI_PRIMARY_BUS   0x18 /* Primary bus number */
 
#define PCI_SECONDARY_BUS   0x19 /* Secondary bus number */
 
#define PCI_SUBORDINATE_BUS   0x1a
 
#define PCI_SEC_LATENCY_TIMER   0x1b
 
#define PCI_IO_BASE   0x1c /* I/O range behind the bridge */
 
#define PCI_IO_LIMIT   0x1d
 
#define PCI_IO_RANGE_TYPE_MASK   0x0f /* I/O bridging type */
 
#define PCI_IO_RANGE_TYPE_16   0x00
 
#define PCI_IO_RANGE_TYPE_32   0x01
 
#define PCI_IO_RANGE_MASK   ~0x0f
 
#define PCI_SEC_STATUS   0x1e
 
#define PCI_MEMORY_BASE   0x20 /* Memory range behind */
 
#define PCI_MEMORY_LIMIT   0x22
 
#define PCI_MEMORY_RANGE_TYPE_MASK   0x0f
 
#define PCI_MEMORY_RANGE_MASK   ~0x0f
 
#define PCI_PREF_MEMORY_BASE   0x24 /* Prefetchable memory range behind */
 
#define PCI_PREF_MEMORY_LIMIT   0x26
 
#define PCI_PREF_RANGE_TYPE_MASK   0x0f
 
#define PCI_PREF_RANGE_TYPE_32   0x00
 
#define PCI_PREF_RANGE_TYPE_64   0x01
 
#define PCI_PREF_RANGE_MASK   ~0x0f
 
#define PCI_PREF_BASE_UPPER32   0x28
 
#define PCI_PREF_LIMIT_UPPER32   0x2c
 
#define PCI_IO_BASE_UPPER16   0x30 /* Upper half of I/O addresses */
 
#define PCI_IO_LIMIT_UPPER16   0x32
 
#define PCI_ROM_ADDRESS1   0x38
 
#define PCI_BRIDGE_CONTROL   0x3e
 
#define PCI_BRIDGE_CTL_PARITY   0x01
 
#define PCI_BRIDGE_CTL_SERR   0x02 /* The same for SERR forwarding */
 
#define PCI_BRIDGE_CTL_ISA   0x04 /* Disable bridging of ISA ports */
 
#define PCI_BRIDGE_CTL_VGA   0x08 /* Forward VGA addresses */
 
#define PCI_BRIDGE_CTL_VGA16   0x10 /* Enable 16-bit i/o port decoding */
 
#define PCI_BRIDGE_CTL_MASTER_ABORT   0x20 /* Report master aborts */
 
#define PCI_BRIDGE_CTL_BUS_RESET   0x40 /* Secondary bus reset */
 
#define PCI_BRIDGE_CTL_FAST_BACK   0x80
 
#define PCI_CB_CAPABILITY_LIST   0x14
 
#define PCI_CB_SEC_STATUS   0x16 /* Secondary status */
 
#define PCI_CB_PRIMARY_BUS   0x18 /* PCI bus number */
 
#define PCI_CB_CARD_BUS   0x19 /* CardBus bus number */
 
#define PCI_CB_SUBORDINATE_BUS   0x1a /* Subordinate bus number */
 
#define PCI_CB_LATENCY_TIMER   0x1b /* CardBus latency timer */
 
#define PCI_CB_MEMORY_BASE_0   0x1c
 
#define PCI_CB_MEMORY_LIMIT_0   0x20
 
#define PCI_CB_MEMORY_BASE_1   0x24
 
#define PCI_CB_MEMORY_LIMIT_1   0x28
 
#define PCI_CB_IO_BASE_0   0x2c
 
#define PCI_CB_IO_BASE_0_HI   0x2e
 
#define PCI_CB_IO_LIMIT_0   0x30
 
#define PCI_CB_IO_LIMIT_0_HI   0x32
 
#define PCI_CB_IO_BASE_1   0x34
 
#define PCI_CB_IO_BASE_1_HI   0x36
 
#define PCI_CB_IO_LIMIT_1   0x38
 
#define PCI_CB_IO_LIMIT_1_HI   0x3a
 
#define PCI_CB_IO_RANGE_MASK   ~0x03
 
#define PCI_CB_BRIDGE_CONTROL   0x3e
 
#define PCI_CB_BRIDGE_CTL_PARITY   0x01
 
#define PCI_CB_BRIDGE_CTL_SERR   0x02
 
#define PCI_CB_BRIDGE_CTL_ISA   0x04
 
#define PCI_CB_BRIDGE_CTL_VGA   0x08
 
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT   0x20
 
#define PCI_CB_BRIDGE_CTL_CB_RESET   0x40 /* CardBus reset */
 
#define PCI_CB_BRIDGE_CTL_16BIT_INT   0x80
 
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0   0x100
 
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1   0x200
 
#define PCI_CB_BRIDGE_CTL_POST_WRITES   0x400
 
#define PCI_CB_SUBSYSTEM_VENDOR_ID   0x40
 
#define PCI_CB_SUBSYSTEM_ID   0x42
 
#define PCI_CB_LEGACY_MODE_BASE   0x44
 
#define PCI_CAP_LIST_ID   0 /* Capability ID */
 
#define PCI_CAP_ID_PM   0x01 /* Power Management */
 
#define PCI_CAP_ID_AGP   0x02 /* Accelerated Graphics Port */
 
#define PCI_CAP_ID_VPD   0x03 /* Vital Product Data */
 
#define PCI_CAP_ID_SLOTID   0x04 /* Slot Identification */
 
#define PCI_CAP_ID_MSI   0x05 /* Message Signaled Interrupts */
 
#define PCI_CAP_ID_CHSWP   0x06 /* CompactPCI HotSwap */
 
#define PCI_CAP_ID_PCIX   0x07 /* PCIX */
 
#define PCI_CAP_ID_HT   0x08 /* Hypertransport */
 
#define PCI_CAP_ID_EHCI_DEBUG   0x0A /* EHCI debug port */
 
#define PCI_CAP_ID_SHPC   0x0C /* PCI Standard Hot-Plug Controller */
 
#define PCI_CAP_ID_SSVID   0x0D /* Bridge subsystem vendor/device ID */
 
#define PCI_CAP_ID_PCIE   0x10 /* PCI Express */
 
#define PCI_CAP_ID_MSIX   0x11 /* MSI-X */
 
#define PCI_CAP_LIST_NEXT   1 /* Next capability in the list */
 
#define PCI_CAP_FLAGS   2 /* Capability defined flags (16 bits) */
 
#define PCI_HT_CAP_SIZEOF   4
 
#define PCI_HT_CAP_HOST_CTRL   4 /* Host link control */
 
#define PCI_HT_CAP_HOST_WIDTH   6 /* width value & capability */
 
#define PCI_HT_CAP_HOST_FREQ   0x09 /* Host frequency */
 
#define PCI_HT_CAP_HOST_FREQ_CAP   0x0a /* Host Frequency capability */
 
#define PCI_HT_CAP_SLAVE_CTRL0   4 /* link control */
 
#define PCI_HT_CAP_SLAVE_CTRL1   8 /* link control to */
 
#define PCI_HT_CAP_SLAVE_WIDTH0   6 /* width value & capability */
 
#define PCI_HT_CAP_SLAVE_WIDTH1   0x0a /* width value & capability to */
 
#define PCI_HT_CAP_SLAVE_FREQ0   0x0d /* Slave frequency from */
 
#define PCI_HT_CAP_SLAVE_FREQ1   0x011 /* Slave frequency to */
 
#define PCI_HT_CAP_SLAVE_FREQ_CAP0   0x0e /* Frequency capability from */
 
#define PCI_HT_CAP_SLAVE_FREQ_CAP1   0x12 /* Frequency capability to */
 
#define PCI_HT_CAP_SLAVE_LINK_ENUM   0x14 /* Link Enumeration Scratchpad */
 
#define PCI_PM_PMC   2 /* PM Capabilities Register */
 
#define PCI_PM_CAP_VER_MASK   0x0007 /* Version */
 
#define PCI_PM_CAP_PME_CLOCK   0x0008 /* PME clock required */
 
#define PCI_PM_CAP_AUX_POWER   0x0010 /* Auxiliary power support */
 
#define PCI_PM_CAP_DSI   0x0020 /* Device specific initialization */
 
#define PCI_PM_CAP_D1   0x0200 /* D1 power state support */
 
#define PCI_PM_CAP_D2   0x0400 /* D2 power state support */
 
#define PCI_PM_CAP_PME   0x0800 /* PME pin supported */
 
#define PCI_PM_CTRL   4 /* PM control and status register */
 
#define PCI_PM_CTRL_STATE_MASK   0x0003 /* Current power state (D0 to D3) */
 
#define PCI_PM_CTRL_POWER_STATE_D0   0x0
 
#define PCI_PM_CTRL_POWER_STATE_D1   0x1
 
#define PCI_PM_CTRL_POWER_STATE_D2   0x2
 
#define PCI_PM_CTRL_POWER_STATE_D3HOT   0x3
 
#define PCI_PM_CTRL_PME_ENABLE   0x0100 /* PME pin enable */
 
#define PCI_PM_CTRL_DATA_SEL_MASK   0x1e00 /* Data select (??) */
 
#define PCI_PM_CTRL_DATA_SCALE_MASK   0x6000 /* Data scale (??) */
 
#define PCI_PM_CTRL_PME_STATUS   0x8000 /* PME pin status */
 
#define PCI_PM_PPB_EXTENSIONS   6 /* PPB support extensions (??) */
 
#define PCI_PM_PPB_B2_B3   0x40 /* Stop clock when in D3hot (??) */
 
#define PCI_PM_BPCC_ENABLE   0x80
 
#define PCI_PM_DATA_REGISTER   7 /* (??) */
 
#define PCI_PM_SIZEOF   8
 
#define PCI_AGP_VERSION   2 /* BCD version number */
 
#define PCI_AGP_RFU   3 /* Rest of capability flags */
 
#define PCI_AGP_STATUS   4 /* Status register */
 
#define PCI_AGP_STATUS_RQ_MASK   0xff000000
 
#define PCI_AGP_STATUS_SBA   0x0200 /* Sideband addressing supported */
 
#define PCI_AGP_STATUS_64BIT   0x0020 /* 64-bit addressing supported */
 
#define PCI_AGP_STATUS_FW   0x0010 /* FW transfers supported */
 
#define PCI_AGP_STATUS_RATE4   0x0004 /* 4x transfer rate supported */
 
#define PCI_AGP_STATUS_RATE2   0x0002 /* 2x transfer rate supported */
 
#define PCI_AGP_STATUS_RATE1   0x0001 /* 1x transfer rate supported */
 
#define PCI_AGP_COMMAND   8 /* Control register */
 
#define PCI_AGP_COMMAND_RQ_MASK   0xff000000
 
#define PCI_AGP_COMMAND_SBA   0x0200 /* Sideband addressing enabled */
 
#define PCI_AGP_COMMAND_AGP   0x0100
 
#define PCI_AGP_COMMAND_64BIT   0x0020
 
#define PCI_AGP_COMMAND_FW   0x0010 /* Force FW transfers */
 
#define PCI_AGP_COMMAND_RATE4   0x0004 /* Use 4x rate */
 
#define PCI_AGP_COMMAND_RATE2   0x0002 /* Use 4x rate */
 
#define PCI_AGP_COMMAND_RATE1   0x0001 /* Use 4x rate */
 
#define PCI_AGP_SIZEOF   12
 
#define PCI_SID_ESR   2 /* Expansion Slot Register */
 
#define PCI_SID_ESR_NSLOTS   0x1f
 
#define PCI_SID_ESR_FIC   0x20 /* First In Chassis Flag */
 
#define PCI_SID_CHASSIS_NR   3 /* Chassis Number */
 
#define PCI_MSI_FLAGS   2 /* Various flags */
 
#define PCI_MSI_FLAGS_64BIT   0x80 /* 64-bit addresses allowed */
 
#define PCI_MSI_FLAGS_QSIZE   0x70 /* Message queue size configured */
 
#define PCI_MSI_FLAGS_QMASK   0x0e /* Maximum queue size available */
 
#define PCI_MSI_FLAGS_ENABLE   0x01 /* MSI feature enabled */
 
#define PCI_MSI_RFU   3 /* Rest of capability flags */
 
#define PCI_MSI_ADDRESS_LO   4 /* Lower 32 bits */
 
#define PCI_MSI_ADDRESS_HI   8
 
#define PCI_MSI_DATA_32   8 /* 16 bits of data for 32-bit devices */
 
#define PCI_MSI_DATA_64   12 /* 16 bits of data for 64-bit devices */
 
#define PCI_MSI_MASK_BIT   16 /* Mask bits register */
 
#define PCI_MSIX_FLAGS   2
 
#define PCI_MSIX_FLAGS_QSIZE   0x7FF /* table size */
 
#define PCI_MSIX_FLAGS_MASKALL   0x4000 /* Mask all vectors for this function */
 
#define PCI_MSIX_FLAGS_ENABLE   0x8000 /* MSI-X enable */
 
#define PCI_MSIX_TABLE   4 /* Table offset */
 
#define PCI_MSIX_PBA   8 /* Pending Bit Array offset */
 
#define PCI_MSIX_PBA_BIR   0x7 /* BAR index */
 
#define PCI_MSIX_PBA_OFFSET   ~0x7 /* Offset into specified BAR */
 
#define PCI_CAP_MSIX_SIZEOF   12 /* size of MSIX registers */
 
#define PCI_CHSWP_CSR   2 /* Control and Status Register */
 
#define PCI_CHSWP_DHA   0x01 /* Device Hiding Arm */
 
#define PCI_CHSWP_EIM   0x02 /* ENUM# Signal Mask */
 
#define PCI_CHSWP_PIE   0x04 /* Pending Insert or Extract */
 
#define PCI_CHSWP_LOO   0x08 /* LED On / Off */
 
#define PCI_CHSWP_PI   0x30 /* Programming Interface */
 
#define PCI_CHSWP_EXT   0x40 /* ENUM# status - extraction */
 
#define PCI_CHSWP_INS   0x80 /* ENUM# status - insertion */
 
#define PCI_X_CMD   2 /* Modes & Features */
 
#define PCI_X_CMD_DPERR_E   0x0001 /* Data Parity Error Recovery Enable */
 
#define PCI_X_CMD_ERO   0x0002 /* Enable Relaxed Ordering */
 
#define PCI_X_CMD_MAX_READ   0x000c /* Max Memory Read Byte Count */
 
#define PCI_X_CMD_MAX_SPLIT   0x0070 /* Max Outstanding Split Transactions */
 
#define PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
 
#define PCI_X_STATUS   4 /* PCI-X capabilities */
 
#define PCI_X_STATUS_DEVFN   0x000000ff /* A copy of devfn */
 
#define PCI_X_STATUS_BUS   0x0000ff00 /* A copy of bus nr */
 
#define PCI_X_STATUS_64BIT   0x00010000 /* 64-bit device */
 
#define PCI_X_STATUS_133MHZ   0x00020000 /* 133 MHz capable */
 
#define PCI_X_STATUS_SPL_DISC   0x00040000 /* Split Completion Discarded */
 
#define PCI_X_STATUS_UNX_SPL   0x00080000
 
#define PCI_X_STATUS_COMPLEX   0x00100000 /* Device Complexity */
 
#define PCI_X_STATUS_MAX_READ   0x00600000
 
#define PCI_X_STATUS_MAX_SPLIT   0x03800000
 
#define PCI_X_STATUS_SPL_ERR   0x20000000
 
#define PCI_X_STATUS_266MHZ   0x40000000 /* 266 MHz capable */
 
#define PCI_X_STATUS_533MHZ   0x80000000 /* 533 MHz capable */
 
#define PCI_X_SEC_STATUS   2 /* Secondary status */
 
#define PCI_X_SSTATUS_64BIT   0x0001
 
#define PCI_X_SSTATUS_133MHZ   0x0002
 
#define PCI_X_SSTATUS_SPL_DISC   0x0004 /* Split Completion Discarded */
 
#define PCI_X_SSTATUS_UNX_SPL   0x0008 /* Unexpected Split Completion */
 
#define PCI_X_SSTATUS_SPL_OVR   0x0010 /* Split Completion Overrun */
 
#define PCI_X_SSTATUS_SPL_DLY   0x0020 /* Split Completion Delayed */
 
#define PCI_X_SSTATUS_MFREQ(x)   (((x) & 0x03c0) >> 6)
 
#define PCI_X_SSTATUS_CONVENTIONAL_PCI   0x0
 
#define PCI_X_SSTATUS_MODE1_66MHZ   0x1
 
#define PCI_X_SSTATUS_MODE1_100MHZ   0x2
 
#define PCI_X_SSTATUS_MODE1_133MHZ   0x3
 
#define PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ   0x9
 
#define PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ   0xa
 
#define PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ   0xb
 
#define PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ   0xd
 
#define PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ   0xe
 
#define PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ   0xf
 
#define PCI_X_SSTATUS_VERSION(x)   (((x) >> 12) & 3) /* Version */
 
#define PCI_X_SSTATUS_266MHZ   0x4000
 
#define PCI_X_SSTAUTS_533MHZ   0x8000
 
#define PCI_EXP_FLAGS   2 /* Capabilities register */
 
#define PCI_EXP_FLAGS_VERS   0x000f /* Capability version */
 
#define PCI_EXP_FLAGS_TYPE   0x00f0 /* Device/Port type */
 
#define PCI_EXP_TYPE_ENDPOINT   0x0 /* Express Endpoint */
 
#define PCI_EXP_TYPE_LEG_END   0x1 /* Legacy Endpoint */
 
#define PCI_EXP_TYPE_ROOT_PORT   0x4 /* Root Port */
 
#define PCI_EXP_TYPE_UPSTREAM   0x5 /* Upstream Port */
 
#define PCI_EXP_TYPE_DOWNSTREAM   0x6 /* Downstream Port */
 
#define PCI_EXP_TYPE_PCI_BRIDGE   0x7 /* PCI/PCI-X Bridge */
 
#define PCI_EXP_TYPE_PCIE_BRIDGE   0x8 /* PCI/PCI-X to PCIe Bridge */
 
#define PCI_EXP_FLAGS_SLOT   0x0100 /* Slot implemented */
 
#define PCI_EXP_FLAGS_IRQ   0x3e00 /* Interrupt message number */
 
#define PCI_EXP_DEVCAP   4 /* Device capabilities */
 
#define PCI_EXP_DEVCAP_PAYLOAD   0x07 /* Max_Payload_Size */
 
#define PCI_EXP_DEVCAP_PHANTOM   0x18 /* Phantom functions */
 
#define PCI_EXP_DEVCAP_EXT_TAG   0x20 /* Extended tags */
 
#define PCI_EXP_DEVCAP_L0S   0x1c0 /* L0s Acceptable Latency */
 
#define PCI_EXP_DEVCAP_L1   0xe00 /* L1 Acceptable Latency */
 
#define PCI_EXP_DEVCAP_ATN_BUT   0x1000 /* Attention Button Present */
 
#define PCI_EXP_DEVCAP_ATN_IND   0x2000 /* Attention Indicator Present */
 
#define PCI_EXP_DEVCAP_PWR_IND   0x4000 /* Power Indicator Present */
 
#define PCI_EXP_DEVCAP_RBER   0x8000 /* Role-Based Error Reporting */
 
#define PCI_EXP_DEVCAP_PWR_VAL   0x3fc0000 /* Slot Power Limit Value */
 
#define PCI_EXP_DEVCAP_PWR_SCL   0xc000000 /* Slot Power Limit Scale */
 
#define PCI_EXP_DEVCTL   8 /* Device Control */
 
#define PCI_EXP_DEVCTL_CERE   0x0001 /* Correctable Error Reporting En. */
 
#define PCI_EXP_DEVCTL_NFERE   0x0002 /* Non-Fatal Error Reporting Enable */
 
#define PCI_EXP_DEVCTL_FERE   0x0004 /* Fatal Error Reporting Enable */
 
#define PCI_EXP_DEVCTL_URRE   0x0008 /* Unsupported Request Reporting En. */
 
#define PCI_EXP_DEVCTL_RELAX_EN   0x0010 /* Enable relaxed ordering */
 
#define PCI_EXP_DEVCTL_PAYLOAD   0x00e0 /* Max_Payload_Size */
 
#define PCI_EXP_DEVCTL_EXT_TAG   0x0100 /* Extended Tag Field Enable */
 
#define PCI_EXP_DEVCTL_PHANTOM   0x0200 /* Phantom Functions Enable */
 
#define PCI_EXP_DEVCTL_AUX_PME   0x0400 /* Auxiliary Power PM Enable */
 
#define PCI_EXP_DEVCTL_NOSNOOP_EN   0x0800 /* Enable No Snoop */
 
#define PCI_EXP_DEVCTL_READRQ   0x7000 /* Max_Read_Request_Size */
 
#define PCI_EXP_DEVSTA   10 /* Device Status */
 
#define PCI_EXP_DEVSTA_CED   0x01 /* Correctable Error Detected */
 
#define PCI_EXP_DEVSTA_NFED   0x02 /* Non-Fatal Error Detected */
 
#define PCI_EXP_DEVSTA_FED   0x04 /* Fatal Error Detected */
 
#define PCI_EXP_DEVSTA_URD   0x08 /* Unsupported Request Detected */
 
#define PCI_EXP_DEVSTA_AUXPD   0x10 /* AUX Power Detected */
 
#define PCI_EXP_DEVSTA_TRPND   0x20 /* Transactions Pending */
 
#define PCI_EXP_LNKCAP   12 /* Link Capabilities */
 
#define PCI_EXP_LNKCAP_ASPMS   0xc00 /* ASPM Support */
 
#define PCI_EXP_LNKCAP_L0SEL   0x7000 /* L0s Exit Latency */
 
#define PCI_EXP_LNKCAP_L1EL   0x38000 /* L1 Exit Latency */
 
#define PCI_EXP_CLK_PM   0x40000 /* Clock Power Management */
 
#define PCI_EXP_LNKCAP_PORT   0xff000000 /* Port Number */
 
#define PCI_EXP_LNKCTL   16 /* Link Control */
 
#define PCI_EXP_LNKCTL_RL   0x20 /* Retrain Link */
 
#define PCI_EXP_LNKCTL_CCC   0x40 /* Common Clock COnfiguration */
 
#define PCI_EXP_EN_CLK_PM   0x100 /* Enable Clock Power Management */
 
#define PCI_EXP_LNKSTA   18 /* Link Status */
 
#define PCI_EXP_LNKSTA_LT   0x800 /* Link Training */
 
#define PCI_EXP_LNKSTA_SLC   0x1000 /* Slot Clock Configuration */
 
#define PCI_EXP_SLTCAP   20 /* Slot Capabilities */
 
#define PCI_EXP_SLTCAP_HPC   0x0040 /* Hot-Plug Capable */
 
#define PCI_EXP_SLTCTL   24 /* Slot Control */
 
#define PCI_EXP_SLTSTA   26 /* Slot Status */
 
#define PCI_EXP_RTCTL   28 /* Root Control */
 
#define PCI_EXP_RTCTL_SECEE   0x01 /* System Error on Correctable Error */
 
#define PCI_EXP_RTCTL_SENFEE   0x02 /* System Error on Non-Fatal Error */
 
#define PCI_EXP_RTCTL_SEFEE   0x04 /* System Error on Fatal Error */
 
#define PCI_EXP_RTCTL_PMEIE   0x08 /* PME Interrupt Enable */
 
#define PCI_EXP_RTCTL_CRSSVE   0x10 /* CRS Software Visibility Enable */
 
#define PCI_EXP_RTCAP   30 /* Root Capabilities */
 
#define PCI_EXP_RTSTA   32 /* Root Status */
 
#define PCI_EXP_DEVCAP2   36 /* Device capabilities 2 */
 
#define PCI_EXP_DEVCAP2_LTR   0x0800 /* LTR supported */
 
#define PCI_EXP_DEVCTL2   40 /* Device Control 2 */
 
#define PCI_EXP_DEV2_LTR   0x0400 /* LTR enabled */
 
#define PCI_EXT_CAP_ID(header)   (header & 0x0000ffff)
 
#define PCI_EXT_CAP_VER(header)   ((header >> 16) & 0xf)
 
#define PCI_EXT_CAP_NEXT(header)   ((header >> 20) & 0xffc)
 
#define PCI_EXT_CAP_ID_ERR   1
 
#define PCI_EXT_CAP_ID_VC   2
 
#define PCI_EXT_CAP_ID_DSN   3
 
#define PCI_EXT_CAP_ID_PWR   4
 
#define PCIE_EXT_CAP_OFFSET   0x100
 
#define PCIE_EXT_CAP_AER_ID   0x0001
 
#define PCIE_EXT_CAP_L1SS_ID   0x001E
 
#define PCIE_EXT_CAP_LTR_ID   0x0018
 
#define PCIE_EXT_CAP_RESIZABLE_BAR   0x0015
 
#define PCI_ERR_UNCOR_STATUS   4 /* Uncorrectable Error Status */
 
#define PCI_ERR_UNC_TRAIN   0x00000001 /* Training */
 
#define PCI_ERR_UNC_DLP   0x00000010 /* Data Link Protocol */
 
#define PCI_ERR_UNC_POISON_TLP   0x00001000 /* Poisoned TLP */
 
#define PCI_ERR_UNC_FCP   0x00002000 /* Flow Control Protocol */
 
#define PCI_ERR_UNC_COMP_TIME   0x00004000 /* Completion Timeout */
 
#define PCI_ERR_UNC_COMP_ABORT   0x00008000 /* Completer Abort */
 
#define PCI_ERR_UNC_UNX_COMP   0x00010000 /* Unexpected Completion */
 
#define PCI_ERR_UNC_RX_OVER   0x00020000 /* Receiver Overflow */
 
#define PCI_ERR_UNC_MALF_TLP   0x00040000 /* Malformed TLP */
 
#define PCI_ERR_UNC_ECRC   0x00080000 /* ECRC Error Status */
 
#define PCI_ERR_UNC_UNSUP   0x00100000 /* Unsupported Request */
 
#define PCI_ERR_UNCOR_MASK   8 /* Uncorrectable Error Mask */
 
#define PCI_ERR_UNCOR_SEVER   12 /* Uncorrectable Error Severity */
 
#define PCI_ERR_COR_STATUS   16 /* Correctable Error Status */
 
#define PCI_ERR_COR_RCVR   0x00000001 /* Receiver Error Status */
 
#define PCI_ERR_COR_BAD_TLP   0x00000040 /* Bad TLP Status */
 
#define PCI_ERR_COR_BAD_DLLP   0x00000080 /* Bad DLLP Status */
 
#define PCI_ERR_COR_REP_ROLL   0x00000100 /* REPLAY_NUM Rollover */
 
#define PCI_ERR_COR_REP_TIMER   0x00001000 /* Replay Timer Timeout */
 
#define PCI_ERR_COR_MASK   20 /* Correctable Error Mask */
 
#define PCI_ERR_CAP   24 /* Advanced Error Capabilities */
 
#define PCI_ERR_CAP_FEP(x)   ((x) & 31) /* First Error Pointer */
 
#define PCI_ERR_CAP_ECRC_GENC   0x00000020 /* ECRC Generation Capable */
 
#define PCI_ERR_CAP_ECRC_GENE   0x00000040 /* ECRC Generation Enable */
 
#define PCI_ERR_CAP_ECRC_CHKC   0x00000080 /* ECRC Check Capable */
 
#define PCI_ERR_CAP_ECRC_CHKE   0x00000100 /* ECRC Check Enable */
 
#define PCI_ERR_HEADER_LOG   28 /* Header Log Register (16 bytes) */
 
#define PCI_ERR_ROOT_COMMAND   44 /* Root Error Command */
 
#define PCI_ERR_ROOT_STATUS   48
 
#define PCI_ERR_ROOT_COR_SRC   52
 
#define PCI_ERR_ROOT_SRC   54
 
#define PCI_VC_PORT_REG1   4
 
#define PCI_VC_PORT_REG2   8
 
#define PCI_VC_PORT_CTRL   12
 
#define PCI_VC_PORT_STATUS   14
 
#define PCI_VC_RES_CAP   16
 
#define PCI_VC_RES_CTRL   20
 
#define PCI_VC_RES_STATUS   26
 
#define PCI_PWR_DSR   4 /* Data Select Register */
 
#define PCI_PWR_DATA   8 /* Data Register */
 
#define PCI_PWR_DATA_BASE(x)   ((x) & 0xff) /* Base Power */
 
#define PCI_PWR_DATA_SCALE(x)   (((x) >> 8) & 3) /* Data Scale */
 
#define PCI_PWR_DATA_PM_SUB(x)   (((x) >> 10) & 7) /* PM Sub State */
 
#define PCI_PWR_DATA_PM_STATE(x)   (((x) >> 13) & 3) /* PM State */
 
#define PCI_PWR_DATA_TYPE(x)   (((x) >> 15) & 7) /* Type */
 
#define PCI_PWR_DATA_RAIL(x)   (((x) >> 18) & 7) /* Power Rail */
 
#define PCI_PWR_CAP   12 /* Capability */
 
#define PCI_PWR_CAP_BUDGET(x)   ((x) & 1) /* Included in system budget */
 
#define PCI_LTR_MAX_SNOOP   4
 
#define PCI_LTR_MAX_NOSNOOP   6
 
#define PCI_REBAR_CAP_OFFSET   0x4
 
#define PCI_REBAR_CAP_SIZE_MASK   0xfffffff0
 
#define PCI_REBAR_CTRL_OFFSET   0x8
 
#define PCI_REBAR_CTRL_NBARS_MASK   0xe0
 
#define PCI_REBAR_CTRL_NBARS_SHIFT   5
 
#define PCI_REBAR_CTRL_IDX_MASK   0x07
 
#define PCI_REBAR_CTRL_SIZE_MASK   0xffff0000
 
#define PCI_REBAR_CTRL_SIZE_SHIFT   16
 
#define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
 
#define PCI_SLOT(devfn)   (((devfn) >> 3) & 0x1f)
 
#define PCI_FUNC(devfn)   ((devfn) & 0x07)
 
#define PCI_DEV2DEVFN(sdev)   (((sdev)>>12) & 0xff)
 
#define PCI_DEV2SEGBUS(sdev)   (((sdev)>>20) & 0xfff)
 

Macro Definition Documentation

◆ PCI_AGP_COMMAND

#define PCI_AGP_COMMAND   8 /* Control register */

Definition at line 263 of file pci_def.h.

◆ PCI_AGP_COMMAND_64BIT

#define PCI_AGP_COMMAND_64BIT   0x0020

Definition at line 270 of file pci_def.h.

◆ PCI_AGP_COMMAND_AGP

#define PCI_AGP_COMMAND_AGP   0x0100

Definition at line 268 of file pci_def.h.

◆ PCI_AGP_COMMAND_FW

#define PCI_AGP_COMMAND_FW   0x0010 /* Force FW transfers */

Definition at line 271 of file pci_def.h.

◆ PCI_AGP_COMMAND_RATE1

#define PCI_AGP_COMMAND_RATE1   0x0001 /* Use 4x rate */

Definition at line 274 of file pci_def.h.

◆ PCI_AGP_COMMAND_RATE2

#define PCI_AGP_COMMAND_RATE2   0x0002 /* Use 4x rate */

Definition at line 273 of file pci_def.h.

◆ PCI_AGP_COMMAND_RATE4

#define PCI_AGP_COMMAND_RATE4   0x0004 /* Use 4x rate */

Definition at line 272 of file pci_def.h.

◆ PCI_AGP_COMMAND_RQ_MASK

#define PCI_AGP_COMMAND_RQ_MASK   0xff000000

Definition at line 265 of file pci_def.h.

◆ PCI_AGP_COMMAND_SBA

#define PCI_AGP_COMMAND_SBA   0x0200 /* Sideband addressing enabled */

Definition at line 266 of file pci_def.h.

◆ PCI_AGP_RFU

#define PCI_AGP_RFU   3 /* Rest of capability flags */

Definition at line 253 of file pci_def.h.

◆ PCI_AGP_SIZEOF

#define PCI_AGP_SIZEOF   12

Definition at line 275 of file pci_def.h.

◆ PCI_AGP_STATUS

#define PCI_AGP_STATUS   4 /* Status register */

Definition at line 254 of file pci_def.h.

◆ PCI_AGP_STATUS_64BIT

#define PCI_AGP_STATUS_64BIT   0x0020 /* 64-bit addressing supported */

Definition at line 258 of file pci_def.h.

◆ PCI_AGP_STATUS_FW

#define PCI_AGP_STATUS_FW   0x0010 /* FW transfers supported */

Definition at line 259 of file pci_def.h.

◆ PCI_AGP_STATUS_RATE1

#define PCI_AGP_STATUS_RATE1   0x0001 /* 1x transfer rate supported */

Definition at line 262 of file pci_def.h.

◆ PCI_AGP_STATUS_RATE2

#define PCI_AGP_STATUS_RATE2   0x0002 /* 2x transfer rate supported */

Definition at line 261 of file pci_def.h.

◆ PCI_AGP_STATUS_RATE4

#define PCI_AGP_STATUS_RATE4   0x0004 /* 4x transfer rate supported */

Definition at line 260 of file pci_def.h.

◆ PCI_AGP_STATUS_RQ_MASK

#define PCI_AGP_STATUS_RQ_MASK   0xff000000

Definition at line 256 of file pci_def.h.

◆ PCI_AGP_STATUS_SBA

#define PCI_AGP_STATUS_SBA   0x0200 /* Sideband addressing supported */

Definition at line 257 of file pci_def.h.

◆ PCI_AGP_VERSION

#define PCI_AGP_VERSION   2 /* BCD version number */

Definition at line 252 of file pci_def.h.

◆ PCI_BASE_ADDRESS_0

#define PCI_BASE_ADDRESS_0   0x10 /* 32 bits */

Definition at line 63 of file pci_def.h.

◆ PCI_BASE_ADDRESS_1

#define PCI_BASE_ADDRESS_1   0x14 /* 32 bits [htype 0,1 only] */

Definition at line 64 of file pci_def.h.

◆ PCI_BASE_ADDRESS_2

#define PCI_BASE_ADDRESS_2   0x18 /* 32 bits [htype 0 only] */

Definition at line 65 of file pci_def.h.

◆ PCI_BASE_ADDRESS_3

#define PCI_BASE_ADDRESS_3   0x1c /* 32 bits */

Definition at line 66 of file pci_def.h.

◆ PCI_BASE_ADDRESS_4

#define PCI_BASE_ADDRESS_4   0x20 /* 32 bits */

Definition at line 67 of file pci_def.h.

◆ PCI_BASE_ADDRESS_5

#define PCI_BASE_ADDRESS_5   0x24 /* 32 bits */

Definition at line 68 of file pci_def.h.

◆ PCI_BASE_ADDRESS_IO_ATTR_MASK

#define PCI_BASE_ADDRESS_IO_ATTR_MASK   0x03

Definition at line 78 of file pci_def.h.

◆ PCI_BASE_ADDRESS_MEM_ATTR_MASK

#define PCI_BASE_ADDRESS_MEM_ATTR_MASK   0x0f

Definition at line 77 of file pci_def.h.

◆ PCI_BASE_ADDRESS_MEM_LIMIT_1M

#define PCI_BASE_ADDRESS_MEM_LIMIT_1M   0x02 /* Below 1M [obsolete] */

Definition at line 74 of file pci_def.h.

◆ PCI_BASE_ADDRESS_MEM_LIMIT_32

#define PCI_BASE_ADDRESS_MEM_LIMIT_32   0x00 /* 32 bit address */

Definition at line 73 of file pci_def.h.

◆ PCI_BASE_ADDRESS_MEM_LIMIT_64

#define PCI_BASE_ADDRESS_MEM_LIMIT_64   0x04 /* 64 bit address */

Definition at line 75 of file pci_def.h.

◆ PCI_BASE_ADDRESS_MEM_LIMIT_MASK

#define PCI_BASE_ADDRESS_MEM_LIMIT_MASK   0x06

Definition at line 72 of file pci_def.h.

◆ PCI_BASE_ADDRESS_MEM_PREFETCH

#define PCI_BASE_ADDRESS_MEM_PREFETCH   0x08 /* prefetchable? */

Definition at line 76 of file pci_def.h.

◆ PCI_BASE_ADDRESS_SPACE

#define PCI_BASE_ADDRESS_SPACE   0x01 /* 0 = memory, 1 = I/O */

Definition at line 69 of file pci_def.h.

◆ PCI_BASE_ADDRESS_SPACE_IO

#define PCI_BASE_ADDRESS_SPACE_IO   0x01

Definition at line 70 of file pci_def.h.

◆ PCI_BASE_ADDRESS_SPACE_MEMORY

#define PCI_BASE_ADDRESS_SPACE_MEMORY   0x00

Definition at line 71 of file pci_def.h.

◆ PCI_BIST

#define PCI_BIST   0x0f /* 8 bits */

Definition at line 52 of file pci_def.h.

◆ PCI_BIST_CAPABLE

#define PCI_BIST_CAPABLE   0x80 /* 1 if BIST capable */

Definition at line 55 of file pci_def.h.

◆ PCI_BIST_CODE_MASK

#define PCI_BIST_CODE_MASK   0x0f /* Return result */

Definition at line 53 of file pci_def.h.

◆ PCI_BIST_START

#define PCI_BIST_START   0x40 /* 1 to start BIST, 2 secs or less */

Definition at line 54 of file pci_def.h.

◆ PCI_BRIDGE_CONTROL

#define PCI_BRIDGE_CONTROL   0x3e

Definition at line 134 of file pci_def.h.

◆ PCI_BRIDGE_CTL_BUS_RESET

#define PCI_BRIDGE_CTL_BUS_RESET   0x40 /* Secondary bus reset */

Definition at line 142 of file pci_def.h.

◆ PCI_BRIDGE_CTL_FAST_BACK

#define PCI_BRIDGE_CTL_FAST_BACK   0x80

Definition at line 144 of file pci_def.h.

◆ PCI_BRIDGE_CTL_ISA

#define PCI_BRIDGE_CTL_ISA   0x04 /* Disable bridging of ISA ports */

Definition at line 138 of file pci_def.h.

◆ PCI_BRIDGE_CTL_MASTER_ABORT

#define PCI_BRIDGE_CTL_MASTER_ABORT   0x20 /* Report master aborts */

Definition at line 141 of file pci_def.h.

◆ PCI_BRIDGE_CTL_PARITY

#define PCI_BRIDGE_CTL_PARITY   0x01

Definition at line 136 of file pci_def.h.

◆ PCI_BRIDGE_CTL_SERR

#define PCI_BRIDGE_CTL_SERR   0x02 /* The same for SERR forwarding */

Definition at line 137 of file pci_def.h.

◆ PCI_BRIDGE_CTL_VGA

#define PCI_BRIDGE_CTL_VGA   0x08 /* Forward VGA addresses */

Definition at line 139 of file pci_def.h.

◆ PCI_BRIDGE_CTL_VGA16

#define PCI_BRIDGE_CTL_VGA16   0x10 /* Enable 16-bit i/o port decoding */

Definition at line 140 of file pci_def.h.

◆ PCI_CACHE_LINE_SIZE

#define PCI_CACHE_LINE_SIZE   0x0c /* 8 bits */

Definition at line 45 of file pci_def.h.

◆ PCI_CAP_FLAGS

#define PCI_CAP_FLAGS   2 /* Capability defined flags (16 bits) */

Definition at line 205 of file pci_def.h.

◆ PCI_CAP_ID_AGP

#define PCI_CAP_ID_AGP   0x02 /* Accelerated Graphics Port */

Definition at line 192 of file pci_def.h.

◆ PCI_CAP_ID_CHSWP

#define PCI_CAP_ID_CHSWP   0x06 /* CompactPCI HotSwap */

Definition at line 196 of file pci_def.h.

◆ PCI_CAP_ID_EHCI_DEBUG

#define PCI_CAP_ID_EHCI_DEBUG   0x0A /* EHCI debug port */

Definition at line 199 of file pci_def.h.

◆ PCI_CAP_ID_HT

#define PCI_CAP_ID_HT   0x08 /* Hypertransport */

Definition at line 198 of file pci_def.h.

◆ PCI_CAP_ID_MSI

#define PCI_CAP_ID_MSI   0x05 /* Message Signaled Interrupts */

Definition at line 195 of file pci_def.h.

◆ PCI_CAP_ID_MSIX

#define PCI_CAP_ID_MSIX   0x11 /* MSI-X */

Definition at line 203 of file pci_def.h.

◆ PCI_CAP_ID_PCIE

#define PCI_CAP_ID_PCIE   0x10 /* PCI Express */

Definition at line 202 of file pci_def.h.

◆ PCI_CAP_ID_PCIX

#define PCI_CAP_ID_PCIX   0x07 /* PCIX */

Definition at line 197 of file pci_def.h.

◆ PCI_CAP_ID_PM

#define PCI_CAP_ID_PM   0x01 /* Power Management */

Definition at line 191 of file pci_def.h.

◆ PCI_CAP_ID_SHPC

#define PCI_CAP_ID_SHPC   0x0C /* PCI Standard Hot-Plug Controller */

Definition at line 200 of file pci_def.h.

◆ PCI_CAP_ID_SLOTID

#define PCI_CAP_ID_SLOTID   0x04 /* Slot Identification */

Definition at line 194 of file pci_def.h.

◆ PCI_CAP_ID_SSVID

#define PCI_CAP_ID_SSVID   0x0D /* Bridge subsystem vendor/device ID */

Definition at line 201 of file pci_def.h.

◆ PCI_CAP_ID_VPD

#define PCI_CAP_ID_VPD   0x03 /* Vital Product Data */

Definition at line 193 of file pci_def.h.

◆ PCI_CAP_LIST_ID

#define PCI_CAP_LIST_ID   0 /* Capability ID */

Definition at line 190 of file pci_def.h.

◆ PCI_CAP_LIST_NEXT

#define PCI_CAP_LIST_NEXT   1 /* Next capability in the list */

Definition at line 204 of file pci_def.h.

◆ PCI_CAP_MSIX_SIZEOF

#define PCI_CAP_MSIX_SIZEOF   12 /* size of MSIX registers */

Definition at line 309 of file pci_def.h.

◆ PCI_CAPABILITY_LIST

#define PCI_CAPABILITY_LIST   0x34

Definition at line 91 of file pci_def.h.

◆ PCI_CARDBUS_CIS

#define PCI_CARDBUS_CIS   0x28

Definition at line 82 of file pci_def.h.

◆ PCI_CB_BRIDGE_CONTROL

#define PCI_CB_BRIDGE_CONTROL   0x3e

Definition at line 168 of file pci_def.h.

◆ PCI_CB_BRIDGE_CTL_16BIT_INT

#define PCI_CB_BRIDGE_CTL_16BIT_INT   0x80

Definition at line 177 of file pci_def.h.

◆ PCI_CB_BRIDGE_CTL_CB_RESET

#define PCI_CB_BRIDGE_CTL_CB_RESET   0x40 /* CardBus reset */

Definition at line 175 of file pci_def.h.

◆ PCI_CB_BRIDGE_CTL_ISA

#define PCI_CB_BRIDGE_CTL_ISA   0x04

Definition at line 172 of file pci_def.h.

◆ PCI_CB_BRIDGE_CTL_MASTER_ABORT

#define PCI_CB_BRIDGE_CTL_MASTER_ABORT   0x20

Definition at line 174 of file pci_def.h.

◆ PCI_CB_BRIDGE_CTL_PARITY

#define PCI_CB_BRIDGE_CTL_PARITY   0x01

Definition at line 170 of file pci_def.h.

◆ PCI_CB_BRIDGE_CTL_POST_WRITES

#define PCI_CB_BRIDGE_CTL_POST_WRITES   0x400

Definition at line 181 of file pci_def.h.

◆ PCI_CB_BRIDGE_CTL_PREFETCH_MEM0

#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0   0x100

Definition at line 179 of file pci_def.h.

◆ PCI_CB_BRIDGE_CTL_PREFETCH_MEM1

#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1   0x200

Definition at line 180 of file pci_def.h.

◆ PCI_CB_BRIDGE_CTL_SERR

#define PCI_CB_BRIDGE_CTL_SERR   0x02

Definition at line 171 of file pci_def.h.

◆ PCI_CB_BRIDGE_CTL_VGA

#define PCI_CB_BRIDGE_CTL_VGA   0x08

Definition at line 173 of file pci_def.h.

◆ PCI_CB_CAPABILITY_LIST

#define PCI_CB_CAPABILITY_LIST   0x14

Definition at line 147 of file pci_def.h.

◆ PCI_CB_CARD_BUS

#define PCI_CB_CARD_BUS   0x19 /* CardBus bus number */

Definition at line 151 of file pci_def.h.

◆ PCI_CB_IO_BASE_0

#define PCI_CB_IO_BASE_0   0x2c

Definition at line 158 of file pci_def.h.

◆ PCI_CB_IO_BASE_0_HI

#define PCI_CB_IO_BASE_0_HI   0x2e

Definition at line 159 of file pci_def.h.

◆ PCI_CB_IO_BASE_1

#define PCI_CB_IO_BASE_1   0x34

Definition at line 162 of file pci_def.h.

◆ PCI_CB_IO_BASE_1_HI

#define PCI_CB_IO_BASE_1_HI   0x36

Definition at line 163 of file pci_def.h.

◆ PCI_CB_IO_LIMIT_0

#define PCI_CB_IO_LIMIT_0   0x30

Definition at line 160 of file pci_def.h.

◆ PCI_CB_IO_LIMIT_0_HI

#define PCI_CB_IO_LIMIT_0_HI   0x32

Definition at line 161 of file pci_def.h.

◆ PCI_CB_IO_LIMIT_1

#define PCI_CB_IO_LIMIT_1   0x38

Definition at line 164 of file pci_def.h.

◆ PCI_CB_IO_LIMIT_1_HI

#define PCI_CB_IO_LIMIT_1_HI   0x3a

Definition at line 165 of file pci_def.h.

◆ PCI_CB_IO_RANGE_MASK

#define PCI_CB_IO_RANGE_MASK   ~0x03

Definition at line 166 of file pci_def.h.

◆ PCI_CB_LATENCY_TIMER

#define PCI_CB_LATENCY_TIMER   0x1b /* CardBus latency timer */

Definition at line 153 of file pci_def.h.

◆ PCI_CB_LEGACY_MODE_BASE

#define PCI_CB_LEGACY_MODE_BASE   0x44

Definition at line 185 of file pci_def.h.

◆ PCI_CB_MEMORY_BASE_0

#define PCI_CB_MEMORY_BASE_0   0x1c

Definition at line 154 of file pci_def.h.

◆ PCI_CB_MEMORY_BASE_1

#define PCI_CB_MEMORY_BASE_1   0x24

Definition at line 156 of file pci_def.h.

◆ PCI_CB_MEMORY_LIMIT_0

#define PCI_CB_MEMORY_LIMIT_0   0x20

Definition at line 155 of file pci_def.h.

◆ PCI_CB_MEMORY_LIMIT_1

#define PCI_CB_MEMORY_LIMIT_1   0x28

Definition at line 157 of file pci_def.h.

◆ PCI_CB_PRIMARY_BUS

#define PCI_CB_PRIMARY_BUS   0x18 /* PCI bus number */

Definition at line 150 of file pci_def.h.

◆ PCI_CB_SEC_STATUS

#define PCI_CB_SEC_STATUS   0x16 /* Secondary status */

Definition at line 149 of file pci_def.h.

◆ PCI_CB_SUBORDINATE_BUS

#define PCI_CB_SUBORDINATE_BUS   0x1a /* Subordinate bus number */

Definition at line 152 of file pci_def.h.

◆ PCI_CB_SUBSYSTEM_ID

#define PCI_CB_SUBSYSTEM_ID   0x42

Definition at line 183 of file pci_def.h.

◆ PCI_CB_SUBSYSTEM_VENDOR_ID

#define PCI_CB_SUBSYSTEM_VENDOR_ID   0x40

Definition at line 182 of file pci_def.h.

◆ PCI_CHSWP_CSR

#define PCI_CHSWP_CSR   2 /* Control and Status Register */

Definition at line 313 of file pci_def.h.

◆ PCI_CHSWP_DHA

#define PCI_CHSWP_DHA   0x01 /* Device Hiding Arm */

Definition at line 314 of file pci_def.h.

◆ PCI_CHSWP_EIM

#define PCI_CHSWP_EIM   0x02 /* ENUM# Signal Mask */

Definition at line 315 of file pci_def.h.

◆ PCI_CHSWP_EXT

#define PCI_CHSWP_EXT   0x40 /* ENUM# status - extraction */

Definition at line 319 of file pci_def.h.

◆ PCI_CHSWP_INS

#define PCI_CHSWP_INS   0x80 /* ENUM# status - insertion */

Definition at line 320 of file pci_def.h.

◆ PCI_CHSWP_LOO

#define PCI_CHSWP_LOO   0x08 /* LED On / Off */

Definition at line 317 of file pci_def.h.

◆ PCI_CHSWP_PI

#define PCI_CHSWP_PI   0x30 /* Programming Interface */

Definition at line 318 of file pci_def.h.

◆ PCI_CHSWP_PIE

#define PCI_CHSWP_PIE   0x04 /* Pending Insert or Extract */

Definition at line 316 of file pci_def.h.

◆ PCI_CLASS_DEVICE

#define PCI_CLASS_DEVICE   0x0a /* Device class */

Definition at line 43 of file pci_def.h.

◆ PCI_CLASS_PROG

#define PCI_CLASS_PROG   0x09 /* Reg. Level Programming Interface */

Definition at line 42 of file pci_def.h.

◆ PCI_CLASS_REVISION

#define PCI_CLASS_REVISION
Value:
0x08 /* High 24 bits are class, low 8
revision */

Definition at line 40 of file pci_def.h.

◆ PCI_COMMAND

#define PCI_COMMAND   0x04 /* 16 bits */

Definition at line 10 of file pci_def.h.

◆ PCI_COMMAND_FAST_BACK

#define PCI_COMMAND_FAST_BACK   0x200 /* Enable back-to-back writes */

Definition at line 20 of file pci_def.h.

◆ PCI_COMMAND_INT_DISABLE

#define PCI_COMMAND_INT_DISABLE   0x400 /* Interrupt disable */

Definition at line 21 of file pci_def.h.

◆ PCI_COMMAND_INVALIDATE

#define PCI_COMMAND_INVALIDATE   0x10 /* Use memory write and invalidate */

Definition at line 15 of file pci_def.h.

◆ PCI_COMMAND_IO

#define PCI_COMMAND_IO   0x1 /* Enable response in I/O space */

Definition at line 11 of file pci_def.h.

◆ PCI_COMMAND_MASTER

#define PCI_COMMAND_MASTER   0x4 /* Enable bus mastering */

Definition at line 13 of file pci_def.h.

◆ PCI_COMMAND_MEMORY

#define PCI_COMMAND_MEMORY   0x2 /* Enable response in Memory space */

Definition at line 12 of file pci_def.h.

◆ PCI_COMMAND_PARITY

#define PCI_COMMAND_PARITY   0x40 /* Enable parity checking */

Definition at line 17 of file pci_def.h.

◆ PCI_COMMAND_SERR

#define PCI_COMMAND_SERR   0x100 /* Enable SERR */

Definition at line 19 of file pci_def.h.

◆ PCI_COMMAND_SPECIAL

#define PCI_COMMAND_SPECIAL   0x8 /* Enable response to special cycles */

Definition at line 14 of file pci_def.h.

◆ PCI_COMMAND_VGA_PALETTE

#define PCI_COMMAND_VGA_PALETTE   0x20 /* Enable palette snooping */

Definition at line 16 of file pci_def.h.

◆ PCI_COMMAND_WAIT

#define PCI_COMMAND_WAIT   0x80 /* Enable address/data stepping */

Definition at line 18 of file pci_def.h.

◆ PCI_DEV2DEVFN

#define PCI_DEV2DEVFN (   sdev)    (((sdev)>>12) & 0xff)

Definition at line 553 of file pci_def.h.

◆ PCI_DEV2SEGBUS

#define PCI_DEV2SEGBUS (   sdev)    (((sdev)>>20) & 0xfff)

Definition at line 554 of file pci_def.h.

◆ PCI_DEVFN

#define PCI_DEVFN (   slot,
  func 
)    ((((slot) & 0x1f) << 3) | ((func) & 0x07))

Definition at line 548 of file pci_def.h.

◆ PCI_DEVICE_ID

#define PCI_DEVICE_ID   0x02 /* 16 bits */

Definition at line 9 of file pci_def.h.

◆ PCI_ERR_CAP

#define PCI_ERR_CAP   24 /* Advanced Error Capabilities */

Definition at line 493 of file pci_def.h.

◆ PCI_ERR_CAP_ECRC_CHKC

#define PCI_ERR_CAP_ECRC_CHKC   0x00000080 /* ECRC Check Capable */

Definition at line 497 of file pci_def.h.

◆ PCI_ERR_CAP_ECRC_CHKE

#define PCI_ERR_CAP_ECRC_CHKE   0x00000100 /* ECRC Check Enable */

Definition at line 498 of file pci_def.h.

◆ PCI_ERR_CAP_ECRC_GENC

#define PCI_ERR_CAP_ECRC_GENC   0x00000020 /* ECRC Generation Capable */

Definition at line 495 of file pci_def.h.

◆ PCI_ERR_CAP_ECRC_GENE

#define PCI_ERR_CAP_ECRC_GENE   0x00000040 /* ECRC Generation Enable */

Definition at line 496 of file pci_def.h.

◆ PCI_ERR_CAP_FEP

#define PCI_ERR_CAP_FEP (   x)    ((x) & 31) /* First Error Pointer */

Definition at line 494 of file pci_def.h.

◆ PCI_ERR_COR_BAD_DLLP

#define PCI_ERR_COR_BAD_DLLP   0x00000080 /* Bad DLLP Status */

Definition at line 488 of file pci_def.h.

◆ PCI_ERR_COR_BAD_TLP

#define PCI_ERR_COR_BAD_TLP   0x00000040 /* Bad TLP Status */

Definition at line 487 of file pci_def.h.

◆ PCI_ERR_COR_MASK

#define PCI_ERR_COR_MASK   20 /* Correctable Error Mask */

Definition at line 491 of file pci_def.h.

◆ PCI_ERR_COR_RCVR

#define PCI_ERR_COR_RCVR   0x00000001 /* Receiver Error Status */

Definition at line 486 of file pci_def.h.

◆ PCI_ERR_COR_REP_ROLL

#define PCI_ERR_COR_REP_ROLL   0x00000100 /* REPLAY_NUM Rollover */

Definition at line 489 of file pci_def.h.

◆ PCI_ERR_COR_REP_TIMER

#define PCI_ERR_COR_REP_TIMER   0x00001000 /* Replay Timer Timeout */

Definition at line 490 of file pci_def.h.

◆ PCI_ERR_COR_STATUS

#define PCI_ERR_COR_STATUS   16 /* Correctable Error Status */

Definition at line 485 of file pci_def.h.

◆ PCI_ERR_HEADER_LOG

#define PCI_ERR_HEADER_LOG   28 /* Header Log Register (16 bytes) */

Definition at line 499 of file pci_def.h.

◆ PCI_ERR_ROOT_COMMAND

#define PCI_ERR_ROOT_COMMAND   44 /* Root Error Command */

Definition at line 500 of file pci_def.h.

◆ PCI_ERR_ROOT_COR_SRC

#define PCI_ERR_ROOT_COR_SRC   52

Definition at line 502 of file pci_def.h.

◆ PCI_ERR_ROOT_SRC

#define PCI_ERR_ROOT_SRC   54

Definition at line 503 of file pci_def.h.

◆ PCI_ERR_ROOT_STATUS

#define PCI_ERR_ROOT_STATUS   48

Definition at line 501 of file pci_def.h.

◆ PCI_ERR_UNC_COMP_ABORT

#define PCI_ERR_UNC_COMP_ABORT   0x00008000 /* Completer Abort */

Definition at line 475 of file pci_def.h.

◆ PCI_ERR_UNC_COMP_TIME

#define PCI_ERR_UNC_COMP_TIME   0x00004000 /* Completion Timeout */

Definition at line 474 of file pci_def.h.

◆ PCI_ERR_UNC_DLP

#define PCI_ERR_UNC_DLP   0x00000010 /* Data Link Protocol */

Definition at line 471 of file pci_def.h.

◆ PCI_ERR_UNC_ECRC

#define PCI_ERR_UNC_ECRC   0x00080000 /* ECRC Error Status */

Definition at line 479 of file pci_def.h.

◆ PCI_ERR_UNC_FCP

#define PCI_ERR_UNC_FCP   0x00002000 /* Flow Control Protocol */

Definition at line 473 of file pci_def.h.

◆ PCI_ERR_UNC_MALF_TLP

#define PCI_ERR_UNC_MALF_TLP   0x00040000 /* Malformed TLP */

Definition at line 478 of file pci_def.h.

◆ PCI_ERR_UNC_POISON_TLP

#define PCI_ERR_UNC_POISON_TLP   0x00001000 /* Poisoned TLP */

Definition at line 472 of file pci_def.h.

◆ PCI_ERR_UNC_RX_OVER

#define PCI_ERR_UNC_RX_OVER   0x00020000 /* Receiver Overflow */

Definition at line 477 of file pci_def.h.

◆ PCI_ERR_UNC_TRAIN

#define PCI_ERR_UNC_TRAIN   0x00000001 /* Training */

Definition at line 470 of file pci_def.h.

◆ PCI_ERR_UNC_UNSUP

#define PCI_ERR_UNC_UNSUP   0x00100000 /* Unsupported Request */

Definition at line 480 of file pci_def.h.

◆ PCI_ERR_UNC_UNX_COMP

#define PCI_ERR_UNC_UNX_COMP   0x00010000 /* Unexpected Completion */

Definition at line 476 of file pci_def.h.

◆ PCI_ERR_UNCOR_MASK

#define PCI_ERR_UNCOR_MASK   8 /* Uncorrectable Error Mask */

Definition at line 481 of file pci_def.h.

◆ PCI_ERR_UNCOR_SEVER

#define PCI_ERR_UNCOR_SEVER   12 /* Uncorrectable Error Severity */

Definition at line 483 of file pci_def.h.

◆ PCI_ERR_UNCOR_STATUS

#define PCI_ERR_UNCOR_STATUS   4 /* Uncorrectable Error Status */

Definition at line 469 of file pci_def.h.

◆ PCI_EXP_CLK_PM

#define PCI_EXP_CLK_PM   0x40000 /* Clock Power Management */

Definition at line 425 of file pci_def.h.

◆ PCI_EXP_DEV2_LTR

#define PCI_EXP_DEV2_LTR   0x0400 /* LTR enabled */

Definition at line 449 of file pci_def.h.

◆ PCI_EXP_DEVCAP

#define PCI_EXP_DEVCAP   4 /* Device capabilities */

Definition at line 390 of file pci_def.h.

◆ PCI_EXP_DEVCAP2

#define PCI_EXP_DEVCAP2   36 /* Device capabilities 2 */

Definition at line 446 of file pci_def.h.

◆ PCI_EXP_DEVCAP2_LTR

#define PCI_EXP_DEVCAP2_LTR   0x0800 /* LTR supported */

Definition at line 447 of file pci_def.h.

◆ PCI_EXP_DEVCAP_ATN_BUT

#define PCI_EXP_DEVCAP_ATN_BUT   0x1000 /* Attention Button Present */

Definition at line 396 of file pci_def.h.

◆ PCI_EXP_DEVCAP_ATN_IND

#define PCI_EXP_DEVCAP_ATN_IND   0x2000 /* Attention Indicator Present */

Definition at line 397 of file pci_def.h.

◆ PCI_EXP_DEVCAP_EXT_TAG

#define PCI_EXP_DEVCAP_EXT_TAG   0x20 /* Extended tags */

Definition at line 393 of file pci_def.h.

◆ PCI_EXP_DEVCAP_L0S

#define PCI_EXP_DEVCAP_L0S   0x1c0 /* L0s Acceptable Latency */

Definition at line 394 of file pci_def.h.

◆ PCI_EXP_DEVCAP_L1

#define PCI_EXP_DEVCAP_L1   0xe00 /* L1 Acceptable Latency */

Definition at line 395 of file pci_def.h.

◆ PCI_EXP_DEVCAP_PAYLOAD

#define PCI_EXP_DEVCAP_PAYLOAD   0x07 /* Max_Payload_Size */

Definition at line 391 of file pci_def.h.

◆ PCI_EXP_DEVCAP_PHANTOM

#define PCI_EXP_DEVCAP_PHANTOM   0x18 /* Phantom functions */

Definition at line 392 of file pci_def.h.

◆ PCI_EXP_DEVCAP_PWR_IND

#define PCI_EXP_DEVCAP_PWR_IND   0x4000 /* Power Indicator Present */

Definition at line 398 of file pci_def.h.

◆ PCI_EXP_DEVCAP_PWR_SCL

#define PCI_EXP_DEVCAP_PWR_SCL   0xc000000 /* Slot Power Limit Scale */

Definition at line 401 of file pci_def.h.

◆ PCI_EXP_DEVCAP_PWR_VAL

#define PCI_EXP_DEVCAP_PWR_VAL   0x3fc0000 /* Slot Power Limit Value */

Definition at line 400 of file pci_def.h.

◆ PCI_EXP_DEVCAP_RBER

#define PCI_EXP_DEVCAP_RBER   0x8000 /* Role-Based Error Reporting */

Definition at line 399 of file pci_def.h.

◆ PCI_EXP_DEVCTL

#define PCI_EXP_DEVCTL   8 /* Device Control */

Definition at line 402 of file pci_def.h.

◆ PCI_EXP_DEVCTL2

#define PCI_EXP_DEVCTL2   40 /* Device Control 2 */

Definition at line 448 of file pci_def.h.

◆ PCI_EXP_DEVCTL_AUX_PME

#define PCI_EXP_DEVCTL_AUX_PME   0x0400 /* Auxiliary Power PM Enable */

Definition at line 411 of file pci_def.h.

◆ PCI_EXP_DEVCTL_CERE

#define PCI_EXP_DEVCTL_CERE   0x0001 /* Correctable Error Reporting En. */

Definition at line 403 of file pci_def.h.

◆ PCI_EXP_DEVCTL_EXT_TAG

#define PCI_EXP_DEVCTL_EXT_TAG   0x0100 /* Extended Tag Field Enable */

Definition at line 409 of file pci_def.h.

◆ PCI_EXP_DEVCTL_FERE

#define PCI_EXP_DEVCTL_FERE   0x0004 /* Fatal Error Reporting Enable */

Definition at line 405 of file pci_def.h.

◆ PCI_EXP_DEVCTL_NFERE

#define PCI_EXP_DEVCTL_NFERE   0x0002 /* Non-Fatal Error Reporting Enable */

Definition at line 404 of file pci_def.h.

◆ PCI_EXP_DEVCTL_NOSNOOP_EN

#define PCI_EXP_DEVCTL_NOSNOOP_EN   0x0800 /* Enable No Snoop */

Definition at line 412 of file pci_def.h.

◆ PCI_EXP_DEVCTL_PAYLOAD

#define PCI_EXP_DEVCTL_PAYLOAD   0x00e0 /* Max_Payload_Size */

Definition at line 408 of file pci_def.h.

◆ PCI_EXP_DEVCTL_PHANTOM

#define PCI_EXP_DEVCTL_PHANTOM   0x0200 /* Phantom Functions Enable */

Definition at line 410 of file pci_def.h.

◆ PCI_EXP_DEVCTL_READRQ

#define PCI_EXP_DEVCTL_READRQ   0x7000 /* Max_Read_Request_Size */

Definition at line 413 of file pci_def.h.

◆ PCI_EXP_DEVCTL_RELAX_EN

#define PCI_EXP_DEVCTL_RELAX_EN   0x0010 /* Enable relaxed ordering */

Definition at line 407 of file pci_def.h.

◆ PCI_EXP_DEVCTL_URRE

#define PCI_EXP_DEVCTL_URRE   0x0008 /* Unsupported Request Reporting En. */

Definition at line 406 of file pci_def.h.

◆ PCI_EXP_DEVSTA

#define PCI_EXP_DEVSTA   10 /* Device Status */

Definition at line 414 of file pci_def.h.

◆ PCI_EXP_DEVSTA_AUXPD

#define PCI_EXP_DEVSTA_AUXPD   0x10 /* AUX Power Detected */

Definition at line 419 of file pci_def.h.

◆ PCI_EXP_DEVSTA_CED

#define PCI_EXP_DEVSTA_CED   0x01 /* Correctable Error Detected */

Definition at line 415 of file pci_def.h.

◆ PCI_EXP_DEVSTA_FED

#define PCI_EXP_DEVSTA_FED   0x04 /* Fatal Error Detected */

Definition at line 417 of file pci_def.h.

◆ PCI_EXP_DEVSTA_NFED

#define PCI_EXP_DEVSTA_NFED   0x02 /* Non-Fatal Error Detected */

Definition at line 416 of file pci_def.h.

◆ PCI_EXP_DEVSTA_TRPND

#define PCI_EXP_DEVSTA_TRPND   0x20 /* Transactions Pending */

Definition at line 420 of file pci_def.h.

◆ PCI_EXP_DEVSTA_URD

#define PCI_EXP_DEVSTA_URD   0x08 /* Unsupported Request Detected */

Definition at line 418 of file pci_def.h.

◆ PCI_EXP_EN_CLK_PM

#define PCI_EXP_EN_CLK_PM   0x100 /* Enable Clock Power Management */

Definition at line 430 of file pci_def.h.

◆ PCI_EXP_FLAGS

#define PCI_EXP_FLAGS   2 /* Capabilities register */

Definition at line 378 of file pci_def.h.

◆ PCI_EXP_FLAGS_IRQ

#define PCI_EXP_FLAGS_IRQ   0x3e00 /* Interrupt message number */

Definition at line 389 of file pci_def.h.

◆ PCI_EXP_FLAGS_SLOT

#define PCI_EXP_FLAGS_SLOT   0x0100 /* Slot implemented */

Definition at line 388 of file pci_def.h.

◆ PCI_EXP_FLAGS_TYPE

#define PCI_EXP_FLAGS_TYPE   0x00f0 /* Device/Port type */

Definition at line 380 of file pci_def.h.

◆ PCI_EXP_FLAGS_VERS

#define PCI_EXP_FLAGS_VERS   0x000f /* Capability version */

Definition at line 379 of file pci_def.h.

◆ PCI_EXP_LNKCAP

#define PCI_EXP_LNKCAP   12 /* Link Capabilities */

Definition at line 421 of file pci_def.h.

◆ PCI_EXP_LNKCAP_ASPMS

#define PCI_EXP_LNKCAP_ASPMS   0xc00 /* ASPM Support */

Definition at line 422 of file pci_def.h.

◆ PCI_EXP_LNKCAP_L0SEL

#define PCI_EXP_LNKCAP_L0SEL   0x7000 /* L0s Exit Latency */

Definition at line 423 of file pci_def.h.

◆ PCI_EXP_LNKCAP_L1EL

#define PCI_EXP_LNKCAP_L1EL   0x38000 /* L1 Exit Latency */

Definition at line 424 of file pci_def.h.

◆ PCI_EXP_LNKCAP_PORT

#define PCI_EXP_LNKCAP_PORT   0xff000000 /* Port Number */

Definition at line 426 of file pci_def.h.

◆ PCI_EXP_LNKCTL

#define PCI_EXP_LNKCTL   16 /* Link Control */

Definition at line 427 of file pci_def.h.

◆ PCI_EXP_LNKCTL_CCC

#define PCI_EXP_LNKCTL_CCC   0x40 /* Common Clock COnfiguration */

Definition at line 429 of file pci_def.h.

◆ PCI_EXP_LNKCTL_RL

#define PCI_EXP_LNKCTL_RL   0x20 /* Retrain Link */

Definition at line 428 of file pci_def.h.

◆ PCI_EXP_LNKSTA

#define PCI_EXP_LNKSTA   18 /* Link Status */

Definition at line 431 of file pci_def.h.

◆ PCI_EXP_LNKSTA_LT

#define PCI_EXP_LNKSTA_LT   0x800 /* Link Training */

Definition at line 432 of file pci_def.h.

◆ PCI_EXP_LNKSTA_SLC

#define PCI_EXP_LNKSTA_SLC   0x1000 /* Slot Clock Configuration */

Definition at line 433 of file pci_def.h.

◆ PCI_EXP_RTCAP

#define PCI_EXP_RTCAP   30 /* Root Capabilities */

Definition at line 444 of file pci_def.h.

◆ PCI_EXP_RTCTL

#define PCI_EXP_RTCTL   28 /* Root Control */

Definition at line 438 of file pci_def.h.

◆ PCI_EXP_RTCTL_CRSSVE

#define PCI_EXP_RTCTL_CRSSVE   0x10 /* CRS Software Visibility Enable */

Definition at line 443 of file pci_def.h.

◆ PCI_EXP_RTCTL_PMEIE

#define PCI_EXP_RTCTL_PMEIE   0x08 /* PME Interrupt Enable */

Definition at line 442 of file pci_def.h.

◆ PCI_EXP_RTCTL_SECEE

#define PCI_EXP_RTCTL_SECEE   0x01 /* System Error on Correctable Error */

Definition at line 439 of file pci_def.h.

◆ PCI_EXP_RTCTL_SEFEE

#define PCI_EXP_RTCTL_SEFEE   0x04 /* System Error on Fatal Error */

Definition at line 441 of file pci_def.h.

◆ PCI_EXP_RTCTL_SENFEE

#define PCI_EXP_RTCTL_SENFEE   0x02 /* System Error on Non-Fatal Error */

Definition at line 440 of file pci_def.h.

◆ PCI_EXP_RTSTA

#define PCI_EXP_RTSTA   32 /* Root Status */

Definition at line 445 of file pci_def.h.

◆ PCI_EXP_SLTCAP

#define PCI_EXP_SLTCAP   20 /* Slot Capabilities */

Definition at line 434 of file pci_def.h.

◆ PCI_EXP_SLTCAP_HPC

#define PCI_EXP_SLTCAP_HPC   0x0040 /* Hot-Plug Capable */

Definition at line 435 of file pci_def.h.

◆ PCI_EXP_SLTCTL

#define PCI_EXP_SLTCTL   24 /* Slot Control */

Definition at line 436 of file pci_def.h.

◆ PCI_EXP_SLTSTA

#define PCI_EXP_SLTSTA   26 /* Slot Status */

Definition at line 437 of file pci_def.h.

◆ PCI_EXP_TYPE_DOWNSTREAM

#define PCI_EXP_TYPE_DOWNSTREAM   0x6 /* Downstream Port */

Definition at line 385 of file pci_def.h.

◆ PCI_EXP_TYPE_ENDPOINT

#define PCI_EXP_TYPE_ENDPOINT   0x0 /* Express Endpoint */

Definition at line 381 of file pci_def.h.

◆ PCI_EXP_TYPE_LEG_END

#define PCI_EXP_TYPE_LEG_END   0x1 /* Legacy Endpoint */

Definition at line 382 of file pci_def.h.

◆ PCI_EXP_TYPE_PCI_BRIDGE

#define PCI_EXP_TYPE_PCI_BRIDGE   0x7 /* PCI/PCI-X Bridge */

Definition at line 386 of file pci_def.h.

◆ PCI_EXP_TYPE_PCIE_BRIDGE

#define PCI_EXP_TYPE_PCIE_BRIDGE   0x8 /* PCI/PCI-X to PCIe Bridge */

Definition at line 387 of file pci_def.h.

◆ PCI_EXP_TYPE_ROOT_PORT

#define PCI_EXP_TYPE_ROOT_PORT   0x4 /* Root Port */

Definition at line 383 of file pci_def.h.

◆ PCI_EXP_TYPE_UPSTREAM

#define PCI_EXP_TYPE_UPSTREAM   0x5 /* Upstream Port */

Definition at line 384 of file pci_def.h.

◆ PCI_EXT_CAP_ID

#define PCI_EXT_CAP_ID (   header)    (header & 0x0000ffff)

Definition at line 452 of file pci_def.h.

◆ PCI_EXT_CAP_ID_DSN

#define PCI_EXT_CAP_ID_DSN   3

Definition at line 458 of file pci_def.h.

◆ PCI_EXT_CAP_ID_ERR

#define PCI_EXT_CAP_ID_ERR   1

Definition at line 456 of file pci_def.h.

◆ PCI_EXT_CAP_ID_PWR

#define PCI_EXT_CAP_ID_PWR   4

Definition at line 459 of file pci_def.h.

◆ PCI_EXT_CAP_ID_VC

#define PCI_EXT_CAP_ID_VC   2

Definition at line 457 of file pci_def.h.

◆ PCI_EXT_CAP_NEXT

#define PCI_EXT_CAP_NEXT (   header)    ((header >> 20) & 0xffc)

Definition at line 454 of file pci_def.h.

◆ PCI_EXT_CAP_VER

#define PCI_EXT_CAP_VER (   header)    ((header >> 16) & 0xf)

Definition at line 453 of file pci_def.h.

◆ PCI_FUNC

#define PCI_FUNC (   devfn)    ((devfn) & 0x07)

Definition at line 550 of file pci_def.h.

◆ PCI_HEADER_TYPE

#define PCI_HEADER_TYPE   0x0e /* 8 bits */

Definition at line 47 of file pci_def.h.

◆ PCI_HEADER_TYPE_BRIDGE

#define PCI_HEADER_TYPE_BRIDGE   1

Definition at line 49 of file pci_def.h.

◆ PCI_HEADER_TYPE_CARDBUS

#define PCI_HEADER_TYPE_CARDBUS   2

Definition at line 50 of file pci_def.h.

◆ PCI_HEADER_TYPE_NORMAL

#define PCI_HEADER_TYPE_NORMAL   0

Definition at line 48 of file pci_def.h.

◆ PCI_HT_CAP_HOST_CTRL

#define PCI_HT_CAP_HOST_CTRL   4 /* Host link control */

Definition at line 209 of file pci_def.h.

◆ PCI_HT_CAP_HOST_FREQ

#define PCI_HT_CAP_HOST_FREQ   0x09 /* Host frequency */

Definition at line 211 of file pci_def.h.

◆ PCI_HT_CAP_HOST_FREQ_CAP

#define PCI_HT_CAP_HOST_FREQ_CAP   0x0a /* Host Frequency capability */

Definition at line 212 of file pci_def.h.

◆ PCI_HT_CAP_HOST_WIDTH

#define PCI_HT_CAP_HOST_WIDTH   6 /* width value & capability */

Definition at line 210 of file pci_def.h.

◆ PCI_HT_CAP_SIZEOF

#define PCI_HT_CAP_SIZEOF   4

Definition at line 208 of file pci_def.h.

◆ PCI_HT_CAP_SLAVE_CTRL0

#define PCI_HT_CAP_SLAVE_CTRL0   4 /* link control */

Definition at line 213 of file pci_def.h.

◆ PCI_HT_CAP_SLAVE_CTRL1

#define PCI_HT_CAP_SLAVE_CTRL1   8 /* link control to */

Definition at line 214 of file pci_def.h.

◆ PCI_HT_CAP_SLAVE_FREQ0

#define PCI_HT_CAP_SLAVE_FREQ0   0x0d /* Slave frequency from */

Definition at line 217 of file pci_def.h.

◆ PCI_HT_CAP_SLAVE_FREQ1

#define PCI_HT_CAP_SLAVE_FREQ1   0x011 /* Slave frequency to */

Definition at line 218 of file pci_def.h.

◆ PCI_HT_CAP_SLAVE_FREQ_CAP0

#define PCI_HT_CAP_SLAVE_FREQ_CAP0   0x0e /* Frequency capability from */

Definition at line 219 of file pci_def.h.

◆ PCI_HT_CAP_SLAVE_FREQ_CAP1

#define PCI_HT_CAP_SLAVE_FREQ_CAP1   0x12 /* Frequency capability to */

Definition at line 220 of file pci_def.h.

◆ PCI_HT_CAP_SLAVE_LINK_ENUM

#define PCI_HT_CAP_SLAVE_LINK_ENUM   0x14 /* Link Enumeration Scratchpad */

Definition at line 221 of file pci_def.h.

◆ PCI_HT_CAP_SLAVE_WIDTH0

#define PCI_HT_CAP_SLAVE_WIDTH0   6 /* width value & capability */

Definition at line 215 of file pci_def.h.

◆ PCI_HT_CAP_SLAVE_WIDTH1

#define PCI_HT_CAP_SLAVE_WIDTH1   0x0a /* width value & capability to */

Definition at line 216 of file pci_def.h.

◆ PCI_INTERRUPT_LINE

#define PCI_INTERRUPT_LINE   0x3c /* 8 bits */

Definition at line 94 of file pci_def.h.

◆ PCI_INTERRUPT_PIN

#define PCI_INTERRUPT_PIN   0x3d /* 8 bits */

Definition at line 95 of file pci_def.h.

◆ PCI_IO_BASE

#define PCI_IO_BASE   0x1c /* I/O range behind the bridge */

Definition at line 106 of file pci_def.h.

◆ PCI_IO_BASE_UPPER16

#define PCI_IO_BASE_UPPER16   0x30 /* Upper half of I/O addresses */

Definition at line 127 of file pci_def.h.

◆ PCI_IO_LIMIT

#define PCI_IO_LIMIT   0x1d

Definition at line 107 of file pci_def.h.

◆ PCI_IO_LIMIT_UPPER16

#define PCI_IO_LIMIT_UPPER16   0x32

Definition at line 128 of file pci_def.h.

◆ PCI_IO_RANGE_MASK

#define PCI_IO_RANGE_MASK   ~0x0f

Definition at line 111 of file pci_def.h.

◆ PCI_IO_RANGE_TYPE_16

#define PCI_IO_RANGE_TYPE_16   0x00

Definition at line 109 of file pci_def.h.

◆ PCI_IO_RANGE_TYPE_32

#define PCI_IO_RANGE_TYPE_32   0x01

Definition at line 110 of file pci_def.h.

◆ PCI_IO_RANGE_TYPE_MASK

#define PCI_IO_RANGE_TYPE_MASK   0x0f /* I/O bridging type */

Definition at line 108 of file pci_def.h.

◆ PCI_LATENCY_TIMER

#define PCI_LATENCY_TIMER   0x0d /* 8 bits */

Definition at line 46 of file pci_def.h.

◆ PCI_LTR_MAX_NOSNOOP

#define PCI_LTR_MAX_NOSNOOP   6

Definition at line 528 of file pci_def.h.

◆ PCI_LTR_MAX_SNOOP

#define PCI_LTR_MAX_SNOOP   4

Definition at line 527 of file pci_def.h.

◆ PCI_MAX_LAT

#define PCI_MAX_LAT   0x3f /* 8 bits */

Definition at line 97 of file pci_def.h.

◆ PCI_MEMORY_BASE

#define PCI_MEMORY_BASE   0x20 /* Memory range behind */

Definition at line 114 of file pci_def.h.

◆ PCI_MEMORY_LIMIT

#define PCI_MEMORY_LIMIT   0x22

Definition at line 115 of file pci_def.h.

◆ PCI_MEMORY_RANGE_MASK

#define PCI_MEMORY_RANGE_MASK   ~0x0f

Definition at line 117 of file pci_def.h.

◆ PCI_MEMORY_RANGE_TYPE_MASK

#define PCI_MEMORY_RANGE_TYPE_MASK   0x0f

Definition at line 116 of file pci_def.h.

◆ PCI_MIN_GNT

#define PCI_MIN_GNT   0x3e /* 8 bits */

Definition at line 96 of file pci_def.h.

◆ PCI_MSI_ADDRESS_HI

#define PCI_MSI_ADDRESS_HI   8

Definition at line 295 of file pci_def.h.

◆ PCI_MSI_ADDRESS_LO

#define PCI_MSI_ADDRESS_LO   4 /* Lower 32 bits */

Definition at line 293 of file pci_def.h.

◆ PCI_MSI_DATA_32

#define PCI_MSI_DATA_32   8 /* 16 bits of data for 32-bit devices */

Definition at line 296 of file pci_def.h.

◆ PCI_MSI_DATA_64

#define PCI_MSI_DATA_64   12 /* 16 bits of data for 64-bit devices */

Definition at line 297 of file pci_def.h.

◆ PCI_MSI_FLAGS

#define PCI_MSI_FLAGS   2 /* Various flags */

Definition at line 287 of file pci_def.h.

◆ PCI_MSI_FLAGS_64BIT

#define PCI_MSI_FLAGS_64BIT   0x80 /* 64-bit addresses allowed */

Definition at line 288 of file pci_def.h.

◆ PCI_MSI_FLAGS_ENABLE

#define PCI_MSI_FLAGS_ENABLE   0x01 /* MSI feature enabled */

Definition at line 291 of file pci_def.h.

◆ PCI_MSI_FLAGS_QMASK

#define PCI_MSI_FLAGS_QMASK   0x0e /* Maximum queue size available */

Definition at line 290 of file pci_def.h.

◆ PCI_MSI_FLAGS_QSIZE

#define PCI_MSI_FLAGS_QSIZE   0x70 /* Message queue size configured */

Definition at line 289 of file pci_def.h.

◆ PCI_MSI_MASK_BIT

#define PCI_MSI_MASK_BIT   16 /* Mask bits register */

Definition at line 298 of file pci_def.h.

◆ PCI_MSI_RFU

#define PCI_MSI_RFU   3 /* Rest of capability flags */

Definition at line 292 of file pci_def.h.

◆ PCI_MSIX_FLAGS

#define PCI_MSIX_FLAGS   2

Definition at line 301 of file pci_def.h.

◆ PCI_MSIX_FLAGS_ENABLE

#define PCI_MSIX_FLAGS_ENABLE   0x8000 /* MSI-X enable */

Definition at line 304 of file pci_def.h.

◆ PCI_MSIX_FLAGS_MASKALL

#define PCI_MSIX_FLAGS_MASKALL   0x4000 /* Mask all vectors for this function */

Definition at line 303 of file pci_def.h.

◆ PCI_MSIX_FLAGS_QSIZE

#define PCI_MSIX_FLAGS_QSIZE   0x7FF /* table size */

Definition at line 302 of file pci_def.h.

◆ PCI_MSIX_PBA

#define PCI_MSIX_PBA   8 /* Pending Bit Array offset */

Definition at line 306 of file pci_def.h.

◆ PCI_MSIX_PBA_BIR

#define PCI_MSIX_PBA_BIR   0x7 /* BAR index */

Definition at line 307 of file pci_def.h.

◆ PCI_MSIX_PBA_OFFSET

#define PCI_MSIX_PBA_OFFSET   ~0x7 /* Offset into specified BAR */

Definition at line 308 of file pci_def.h.

◆ PCI_MSIX_TABLE

#define PCI_MSIX_TABLE   4 /* Table offset */

Definition at line 305 of file pci_def.h.

◆ PCI_PM_BPCC_ENABLE

#define PCI_PM_BPCC_ENABLE   0x80

Definition at line 246 of file pci_def.h.

◆ PCI_PM_CAP_AUX_POWER

#define PCI_PM_CAP_AUX_POWER   0x0010 /* Auxiliary power support */

Definition at line 228 of file pci_def.h.

◆ PCI_PM_CAP_D1

#define PCI_PM_CAP_D1   0x0200 /* D1 power state support */

Definition at line 230 of file pci_def.h.

◆ PCI_PM_CAP_D2

#define PCI_PM_CAP_D2   0x0400 /* D2 power state support */

Definition at line 231 of file pci_def.h.

◆ PCI_PM_CAP_DSI

#define PCI_PM_CAP_DSI   0x0020 /* Device specific initialization */

Definition at line 229 of file pci_def.h.

◆ PCI_PM_CAP_PME

#define PCI_PM_CAP_PME   0x0800 /* PME pin supported */

Definition at line 232 of file pci_def.h.

◆ PCI_PM_CAP_PME_CLOCK

#define PCI_PM_CAP_PME_CLOCK   0x0008 /* PME clock required */

Definition at line 227 of file pci_def.h.

◆ PCI_PM_CAP_VER_MASK

#define PCI_PM_CAP_VER_MASK   0x0007 /* Version */

Definition at line 226 of file pci_def.h.

◆ PCI_PM_CTRL

#define PCI_PM_CTRL   4 /* PM control and status register */

Definition at line 233 of file pci_def.h.

◆ PCI_PM_CTRL_DATA_SCALE_MASK

#define PCI_PM_CTRL_DATA_SCALE_MASK   0x6000 /* Data scale (??) */

Definition at line 241 of file pci_def.h.

◆ PCI_PM_CTRL_DATA_SEL_MASK

#define PCI_PM_CTRL_DATA_SEL_MASK   0x1e00 /* Data select (??) */

Definition at line 240 of file pci_def.h.

◆ PCI_PM_CTRL_PME_ENABLE

#define PCI_PM_CTRL_PME_ENABLE   0x0100 /* PME pin enable */

Definition at line 239 of file pci_def.h.

◆ PCI_PM_CTRL_PME_STATUS

#define PCI_PM_CTRL_PME_STATUS   0x8000 /* PME pin status */

Definition at line 242 of file pci_def.h.

◆ PCI_PM_CTRL_POWER_STATE_D0

#define PCI_PM_CTRL_POWER_STATE_D0   0x0

Definition at line 235 of file pci_def.h.

◆ PCI_PM_CTRL_POWER_STATE_D1

#define PCI_PM_CTRL_POWER_STATE_D1   0x1

Definition at line 236 of file pci_def.h.

◆ PCI_PM_CTRL_POWER_STATE_D2

#define PCI_PM_CTRL_POWER_STATE_D2   0x2

Definition at line 237 of file pci_def.h.

◆ PCI_PM_CTRL_POWER_STATE_D3HOT

#define PCI_PM_CTRL_POWER_STATE_D3HOT   0x3

Definition at line 238 of file pci_def.h.

◆ PCI_PM_CTRL_STATE_MASK

#define PCI_PM_CTRL_STATE_MASK   0x0003 /* Current power state (D0 to D3) */

Definition at line 234 of file pci_def.h.

◆ PCI_PM_DATA_REGISTER

#define PCI_PM_DATA_REGISTER   7 /* (??) */

Definition at line 247 of file pci_def.h.

◆ PCI_PM_PMC

#define PCI_PM_PMC   2 /* PM Capabilities Register */

Definition at line 225 of file pci_def.h.

◆ PCI_PM_PPB_B2_B3

#define PCI_PM_PPB_B2_B3   0x40 /* Stop clock when in D3hot (??) */

Definition at line 244 of file pci_def.h.

◆ PCI_PM_PPB_EXTENSIONS

#define PCI_PM_PPB_EXTENSIONS   6 /* PPB support extensions (??) */

Definition at line 243 of file pci_def.h.

◆ PCI_PM_SIZEOF

#define PCI_PM_SIZEOF   8

Definition at line 248 of file pci_def.h.

◆ PCI_PREF_BASE_UPPER32

#define PCI_PREF_BASE_UPPER32   0x28

Definition at line 125 of file pci_def.h.

◆ PCI_PREF_LIMIT_UPPER32

#define PCI_PREF_LIMIT_UPPER32   0x2c

Definition at line 126 of file pci_def.h.

◆ PCI_PREF_MEMORY_BASE

#define PCI_PREF_MEMORY_BASE   0x24 /* Prefetchable memory range behind */

Definition at line 118 of file pci_def.h.

◆ PCI_PREF_MEMORY_LIMIT

#define PCI_PREF_MEMORY_LIMIT   0x26

Definition at line 119 of file pci_def.h.

◆ PCI_PREF_RANGE_MASK

#define PCI_PREF_RANGE_MASK   ~0x0f

Definition at line 123 of file pci_def.h.

◆ PCI_PREF_RANGE_TYPE_32

#define PCI_PREF_RANGE_TYPE_32   0x00

Definition at line 121 of file pci_def.h.

◆ PCI_PREF_RANGE_TYPE_64

#define PCI_PREF_RANGE_TYPE_64   0x01

Definition at line 122 of file pci_def.h.

◆ PCI_PREF_RANGE_TYPE_MASK

#define PCI_PREF_RANGE_TYPE_MASK   0x0f

Definition at line 120 of file pci_def.h.

◆ PCI_PRIMARY_BUS

#define PCI_PRIMARY_BUS   0x18 /* Primary bus number */

Definition at line 100 of file pci_def.h.

◆ PCI_PWR_CAP

#define PCI_PWR_CAP   12 /* Capability */

Definition at line 523 of file pci_def.h.

◆ PCI_PWR_CAP_BUDGET

#define PCI_PWR_CAP_BUDGET (   x)    ((x) & 1) /* Included in system budget */

Definition at line 524 of file pci_def.h.

◆ PCI_PWR_DATA

#define PCI_PWR_DATA   8 /* Data Register */

Definition at line 516 of file pci_def.h.

◆ PCI_PWR_DATA_BASE

#define PCI_PWR_DATA_BASE (   x)    ((x) & 0xff) /* Base Power */

Definition at line 517 of file pci_def.h.

◆ PCI_PWR_DATA_PM_STATE

#define PCI_PWR_DATA_PM_STATE (   x)    (((x) >> 13) & 3) /* PM State */

Definition at line 520 of file pci_def.h.

◆ PCI_PWR_DATA_PM_SUB

#define PCI_PWR_DATA_PM_SUB (   x)    (((x) >> 10) & 7) /* PM Sub State */

Definition at line 519 of file pci_def.h.

◆ PCI_PWR_DATA_RAIL

#define PCI_PWR_DATA_RAIL (   x)    (((x) >> 18) & 7) /* Power Rail */

Definition at line 522 of file pci_def.h.

◆ PCI_PWR_DATA_SCALE

#define PCI_PWR_DATA_SCALE (   x)    (((x) >> 8) & 3) /* Data Scale */

Definition at line 518 of file pci_def.h.

◆ PCI_PWR_DATA_TYPE

#define PCI_PWR_DATA_TYPE (   x)    (((x) >> 15) & 7) /* Type */

Definition at line 521 of file pci_def.h.

◆ PCI_PWR_DSR

#define PCI_PWR_DSR   4 /* Data Select Register */

Definition at line 515 of file pci_def.h.

◆ PCI_REBAR_CAP_OFFSET

#define PCI_REBAR_CAP_OFFSET   0x4

Definition at line 531 of file pci_def.h.

◆ PCI_REBAR_CAP_SIZE_MASK

#define PCI_REBAR_CAP_SIZE_MASK   0xfffffff0

Definition at line 532 of file pci_def.h.

◆ PCI_REBAR_CTRL_IDX_MASK

#define PCI_REBAR_CTRL_IDX_MASK   0x07

Definition at line 536 of file pci_def.h.

◆ PCI_REBAR_CTRL_NBARS_MASK

#define PCI_REBAR_CTRL_NBARS_MASK   0xe0

Definition at line 534 of file pci_def.h.

◆ PCI_REBAR_CTRL_NBARS_SHIFT

#define PCI_REBAR_CTRL_NBARS_SHIFT   5

Definition at line 535 of file pci_def.h.

◆ PCI_REBAR_CTRL_OFFSET

#define PCI_REBAR_CTRL_OFFSET   0x8

Definition at line 533 of file pci_def.h.

◆ PCI_REBAR_CTRL_SIZE_MASK

#define PCI_REBAR_CTRL_SIZE_MASK   0xffff0000

Definition at line 537 of file pci_def.h.

◆ PCI_REBAR_CTRL_SIZE_SHIFT

#define PCI_REBAR_CTRL_SIZE_SHIFT   16

Definition at line 538 of file pci_def.h.

◆ PCI_REVISION_ID

#define PCI_REVISION_ID   0x08 /* Revision ID */

Definition at line 41 of file pci_def.h.

◆ PCI_ROM_ADDRESS

#define PCI_ROM_ADDRESS   0x30

Definition at line 86 of file pci_def.h.

◆ PCI_ROM_ADDRESS1

#define PCI_ROM_ADDRESS1   0x38

Definition at line 132 of file pci_def.h.

◆ PCI_ROM_ADDRESS_ENABLE

#define PCI_ROM_ADDRESS_ENABLE   0x01

Definition at line 87 of file pci_def.h.

◆ PCI_ROM_ADDRESS_MASK

#define PCI_ROM_ADDRESS_MASK   (~0x7ffUL)

Definition at line 88 of file pci_def.h.

◆ PCI_SEC_LATENCY_TIMER

#define PCI_SEC_LATENCY_TIMER   0x1b

Definition at line 105 of file pci_def.h.

◆ PCI_SEC_STATUS

#define PCI_SEC_STATUS   0x1e

Definition at line 113 of file pci_def.h.

◆ PCI_SECONDARY_BUS

#define PCI_SECONDARY_BUS   0x19 /* Secondary bus number */

Definition at line 101 of file pci_def.h.

◆ PCI_SID_CHASSIS_NR

#define PCI_SID_CHASSIS_NR   3 /* Chassis Number */

Definition at line 283 of file pci_def.h.

◆ PCI_SID_ESR

#define PCI_SID_ESR   2 /* Expansion Slot Register */

Definition at line 279 of file pci_def.h.

◆ PCI_SID_ESR_FIC

#define PCI_SID_ESR_FIC   0x20 /* First In Chassis Flag */

Definition at line 282 of file pci_def.h.

◆ PCI_SID_ESR_NSLOTS

#define PCI_SID_ESR_NSLOTS   0x1f

Definition at line 281 of file pci_def.h.

◆ PCI_SLOT

#define PCI_SLOT (   devfn)    (((devfn) >> 3) & 0x1f)

Definition at line 549 of file pci_def.h.

◆ PCI_STATUS

#define PCI_STATUS   0x06 /* 16 bits */

Definition at line 23 of file pci_def.h.

◆ PCI_STATUS_66MHZ

#define PCI_STATUS_66MHZ   0x20 /* Support 66 Mhz PCI 2.1 bus */

Definition at line 25 of file pci_def.h.

◆ PCI_STATUS_CAP_LIST

#define PCI_STATUS_CAP_LIST   0x10 /* Support Capability List */

Definition at line 24 of file pci_def.h.

◆ PCI_STATUS_DETECTED_PARITY

#define PCI_STATUS_DETECTED_PARITY   0x8000 /* Set on parity error */

Definition at line 38 of file pci_def.h.

◆ PCI_STATUS_DEVSEL_FAST

#define PCI_STATUS_DEVSEL_FAST   0x000

Definition at line 31 of file pci_def.h.

◆ PCI_STATUS_DEVSEL_MASK

#define PCI_STATUS_DEVSEL_MASK   0x600 /* DEVSEL timing */

Definition at line 30 of file pci_def.h.

◆ PCI_STATUS_DEVSEL_MEDIUM

#define PCI_STATUS_DEVSEL_MEDIUM   0x200

Definition at line 32 of file pci_def.h.

◆ PCI_STATUS_DEVSEL_SLOW

#define PCI_STATUS_DEVSEL_SLOW   0x400

Definition at line 33 of file pci_def.h.

◆ PCI_STATUS_FAST_BACK

#define PCI_STATUS_FAST_BACK   0x80 /* Accept fast-back to back */

Definition at line 28 of file pci_def.h.

◆ PCI_STATUS_PARITY

#define PCI_STATUS_PARITY   0x100 /* Detected parity error */

Definition at line 29 of file pci_def.h.

◆ PCI_STATUS_REC_MASTER_ABORT

#define PCI_STATUS_REC_MASTER_ABORT   0x2000 /* Set on master abort */

Definition at line 36 of file pci_def.h.

◆ PCI_STATUS_REC_TARGET_ABORT

#define PCI_STATUS_REC_TARGET_ABORT   0x1000 /* Master ack of " */

Definition at line 35 of file pci_def.h.

◆ PCI_STATUS_SIG_SYSTEM_ERROR

#define PCI_STATUS_SIG_SYSTEM_ERROR   0x4000 /* Set when we drive SERR */

Definition at line 37 of file pci_def.h.

◆ PCI_STATUS_SIG_TARGET_ABORT

#define PCI_STATUS_SIG_TARGET_ABORT   0x800 /* Set on target abort */

Definition at line 34 of file pci_def.h.

◆ PCI_STATUS_UDF

#define PCI_STATUS_UDF   0x40

Definition at line 27 of file pci_def.h.

◆ PCI_SUBORDINATE_BUS

#define PCI_SUBORDINATE_BUS   0x1a

Definition at line 103 of file pci_def.h.

◆ PCI_SUBSYSTEM_ID

#define PCI_SUBSYSTEM_ID   0x2e

Definition at line 84 of file pci_def.h.

◆ PCI_SUBSYSTEM_VENDOR_ID

#define PCI_SUBSYSTEM_VENDOR_ID   0x2c

Definition at line 83 of file pci_def.h.

◆ PCI_VC_PORT_CTRL

#define PCI_VC_PORT_CTRL   12

Definition at line 508 of file pci_def.h.

◆ PCI_VC_PORT_REG1

#define PCI_VC_PORT_REG1   4

Definition at line 506 of file pci_def.h.

◆ PCI_VC_PORT_REG2

#define PCI_VC_PORT_REG2   8

Definition at line 507 of file pci_def.h.

◆ PCI_VC_PORT_STATUS

#define PCI_VC_PORT_STATUS   14

Definition at line 509 of file pci_def.h.

◆ PCI_VC_RES_CAP

#define PCI_VC_RES_CAP   16

Definition at line 510 of file pci_def.h.

◆ PCI_VC_RES_CTRL

#define PCI_VC_RES_CTRL   20

Definition at line 511 of file pci_def.h.

◆ PCI_VC_RES_STATUS

#define PCI_VC_RES_STATUS   26

Definition at line 512 of file pci_def.h.

◆ PCI_VENDOR_ID

#define PCI_VENDOR_ID   0x00 /* 16 bits */

Definition at line 8 of file pci_def.h.

◆ PCI_X_CMD

#define PCI_X_CMD   2 /* Modes & Features */

Definition at line 324 of file pci_def.h.

◆ PCI_X_CMD_DPERR_E

#define PCI_X_CMD_DPERR_E   0x0001 /* Data Parity Error Recovery Enable */

Definition at line 325 of file pci_def.h.

◆ PCI_X_CMD_ERO

#define PCI_X_CMD_ERO   0x0002 /* Enable Relaxed Ordering */

Definition at line 326 of file pci_def.h.

◆ PCI_X_CMD_MAX_READ

#define PCI_X_CMD_MAX_READ   0x000c /* Max Memory Read Byte Count */

Definition at line 327 of file pci_def.h.

◆ PCI_X_CMD_MAX_SPLIT

#define PCI_X_CMD_MAX_SPLIT   0x0070 /* Max Outstanding Split Transactions */

Definition at line 328 of file pci_def.h.

◆ PCI_X_CMD_VERSION

#define PCI_X_CMD_VERSION (   x)    (((x) >> 12) & 3) /* Version */

Definition at line 329 of file pci_def.h.

◆ PCI_X_SEC_STATUS

#define PCI_X_SEC_STATUS   2 /* Secondary status */

Definition at line 349 of file pci_def.h.

◆ PCI_X_SSTATUS_133MHZ

#define PCI_X_SSTATUS_133MHZ   0x0002

Definition at line 353 of file pci_def.h.

◆ PCI_X_SSTATUS_266MHZ

#define PCI_X_SSTATUS_266MHZ   0x4000

Definition at line 372 of file pci_def.h.

◆ PCI_X_SSTATUS_64BIT

#define PCI_X_SSTATUS_64BIT   0x0001

Definition at line 351 of file pci_def.h.

◆ PCI_X_SSTATUS_CONVENTIONAL_PCI

#define PCI_X_SSTATUS_CONVENTIONAL_PCI   0x0

Definition at line 360 of file pci_def.h.

◆ PCI_X_SSTATUS_MFREQ

#define PCI_X_SSTATUS_MFREQ (   x)    (((x) & 0x03c0) >> 6)

Definition at line 359 of file pci_def.h.

◆ PCI_X_SSTATUS_MODE1_100MHZ

#define PCI_X_SSTATUS_MODE1_100MHZ   0x2

Definition at line 362 of file pci_def.h.

◆ PCI_X_SSTATUS_MODE1_133MHZ

#define PCI_X_SSTATUS_MODE1_133MHZ   0x3

Definition at line 363 of file pci_def.h.

◆ PCI_X_SSTATUS_MODE1_66MHZ

#define PCI_X_SSTATUS_MODE1_66MHZ   0x1

Definition at line 361 of file pci_def.h.

◆ PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ

#define PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ   0xa

Definition at line 365 of file pci_def.h.

◆ PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ

#define PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ   0xb

Definition at line 366 of file pci_def.h.

◆ PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ

#define PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ   0x9

Definition at line 364 of file pci_def.h.

◆ PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ

#define PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ   0xe

Definition at line 368 of file pci_def.h.

◆ PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ

#define PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ   0xf

Definition at line 369 of file pci_def.h.

◆ PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ

#define PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ   0xd

Definition at line 367 of file pci_def.h.

◆ PCI_X_SSTATUS_SPL_DISC

#define PCI_X_SSTATUS_SPL_DISC   0x0004 /* Split Completion Discarded */

Definition at line 354 of file pci_def.h.

◆ PCI_X_SSTATUS_SPL_DLY

#define PCI_X_SSTATUS_SPL_DLY   0x0020 /* Split Completion Delayed */

Definition at line 357 of file pci_def.h.

◆ PCI_X_SSTATUS_SPL_OVR

#define PCI_X_SSTATUS_SPL_OVR   0x0010 /* Split Completion Overrun */

Definition at line 356 of file pci_def.h.

◆ PCI_X_SSTATUS_UNX_SPL

#define PCI_X_SSTATUS_UNX_SPL   0x0008 /* Unexpected Split Completion */

Definition at line 355 of file pci_def.h.

◆ PCI_X_SSTATUS_VERSION

#define PCI_X_SSTATUS_VERSION (   x)    (((x) >> 12) & 3) /* Version */

Definition at line 370 of file pci_def.h.

◆ PCI_X_SSTAUTS_533MHZ

#define PCI_X_SSTAUTS_533MHZ   0x8000

Definition at line 374 of file pci_def.h.

◆ PCI_X_STATUS

#define PCI_X_STATUS   4 /* PCI-X capabilities */

Definition at line 330 of file pci_def.h.

◆ PCI_X_STATUS_133MHZ

#define PCI_X_STATUS_133MHZ   0x00020000 /* 133 MHz capable */

Definition at line 334 of file pci_def.h.

◆ PCI_X_STATUS_266MHZ

#define PCI_X_STATUS_266MHZ   0x40000000 /* 266 MHz capable */

Definition at line 345 of file pci_def.h.

◆ PCI_X_STATUS_533MHZ

#define PCI_X_STATUS_533MHZ   0x80000000 /* 533 MHz capable */

Definition at line 346 of file pci_def.h.

◆ PCI_X_STATUS_64BIT

#define PCI_X_STATUS_64BIT   0x00010000 /* 64-bit device */

Definition at line 333 of file pci_def.h.

◆ PCI_X_STATUS_BUS

#define PCI_X_STATUS_BUS   0x0000ff00 /* A copy of bus nr */

Definition at line 332 of file pci_def.h.

◆ PCI_X_STATUS_COMPLEX

#define PCI_X_STATUS_COMPLEX   0x00100000 /* Device Complexity */

Definition at line 338 of file pci_def.h.

◆ PCI_X_STATUS_DEVFN

#define PCI_X_STATUS_DEVFN   0x000000ff /* A copy of devfn */

Definition at line 331 of file pci_def.h.

◆ PCI_X_STATUS_MAX_READ

#define PCI_X_STATUS_MAX_READ   0x00600000

Definition at line 340 of file pci_def.h.

◆ PCI_X_STATUS_MAX_SPLIT

#define PCI_X_STATUS_MAX_SPLIT   0x03800000

Definition at line 342 of file pci_def.h.

◆ PCI_X_STATUS_SPL_DISC

#define PCI_X_STATUS_SPL_DISC   0x00040000 /* Split Completion Discarded */

Definition at line 335 of file pci_def.h.

◆ PCI_X_STATUS_SPL_ERR

#define PCI_X_STATUS_SPL_ERR   0x20000000

Definition at line 344 of file pci_def.h.

◆ PCI_X_STATUS_UNX_SPL

#define PCI_X_STATUS_UNX_SPL   0x00080000

Definition at line 337 of file pci_def.h.

◆ PCIE_EXT_CAP_AER_ID

#define PCIE_EXT_CAP_AER_ID   0x0001

Definition at line 463 of file pci_def.h.

◆ PCIE_EXT_CAP_L1SS_ID

#define PCIE_EXT_CAP_L1SS_ID   0x001E

Definition at line 464 of file pci_def.h.

◆ PCIE_EXT_CAP_LTR_ID

#define PCIE_EXT_CAP_LTR_ID   0x0018

Definition at line 465 of file pci_def.h.

◆ PCIE_EXT_CAP_OFFSET

#define PCIE_EXT_CAP_OFFSET   0x100

Definition at line 462 of file pci_def.h.

◆ PCIE_EXT_CAP_RESIZABLE_BAR

#define PCIE_EXT_CAP_RESIZABLE_BAR   0x0015

Definition at line 466 of file pci_def.h.