coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
gpio.h
>
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#include <
soc/mt8183.h
>
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#include <soc/spi.h>
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#include "
early_init.h
"
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#include "
gpio.h
"
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#define BOOTBLOCK_EN_L (GPIO(KPROW0))
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#define AP_IN_SLEEP_L (GPIO(SRCLKENA0))
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void
mainboard_early_init
(
void
)
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{
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mt8183_early_init
();
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/* Turn on real eMMC and allow communication to EC. */
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gpio_output
(
BOOTBLOCK_EN_L
, 1);
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setup_chromeos_gpios
();
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gpio_set_mode
(
AP_IN_SLEEP_L
, PAD_SRCLKENA0_FUNC_SRCLKENA0);
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mtk_spi_init
(CONFIG_DRIVER_TPM_SPI_BUS,
SPI_PAD0_MASK
, 1 *
MHz
, 0);
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gpio_eint_configure
(
CR50_IRQ
,
IRQ_TYPE_EDGE_RISING
);
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}
MHz
#define MHz
Definition:
helpers.h:80
setup_chromeos_gpios
void setup_chromeos_gpios(void)
Definition:
chromeos.c:10
gpio_output
void gpio_output(gpio_t gpio, int value)
Definition:
gpio.c:194
AP_IN_SLEEP_L
#define AP_IN_SLEEP_L
Definition:
early_init.c:11
mainboard_early_init
void mainboard_early_init(void)
Definition:
early_init.c:13
BOOTBLOCK_EN_L
#define BOOTBLOCK_EN_L
Definition:
early_init.c:10
CR50_IRQ
#define CR50_IRQ
Definition:
gpio.h:11
IRQ_TYPE_EDGE_RISING
@ IRQ_TYPE_EDGE_RISING
Definition:
gpio_common.h:55
mt8183.h
mt8183_early_init
void mt8183_early_init(void)
Definition:
mt8183.c:7
gpio_set_mode
void gpio_set_mode(gpio_t gpio, int mode)
Definition:
gpio.c:45
gpio_eint_configure
void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type)
Definition:
gpio.c:142
early_init.h
gpio.h
SPI_PAD0_MASK
@ SPI_PAD0_MASK
Definition:
spi_common.h:46
mtk_spi_init
void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, unsigned int speed_hz, unsigned int tick_dly)
Definition:
spi.c:56
src
mainboard
google
kukui
early_init.c
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