coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <arch/cache.h>
#include <console/console.h>
#include <device/mmio.h>
#include <device/device.h>
#include <ec/google/chromeec/ec.h>
#include <soc/dp.h>
#include <soc/fimd.h>
#include <soc/cpu.h>
#include <soc/clk.h>
#include <string.h>
#include "chip.h"
Go to the source code of this file.
Functions | |
static void | set_cpu_id (void) |
static void | exynos_displayport_init (struct device *dev, u32 lcdbase, unsigned long fb_size) |
static void | tps65090_thru_ec_fet_disable (int index) |
static void | cpu_enable (struct device *dev) |
static void | cpu_read_resources (struct device *dev) |
static void | cpu_init (struct device *dev) |
static void | enable_exynos5420_dev (struct device *dev) |
Variables | |
static unsigned int | cpu_id |
static unsigned int | cpu_rev |
static struct device_operations | cpu_ops |
struct chip_operations | soc_samsung_exynos5420_ops |
Definition at line 113 of file cpu.c.
References exynos_displayport_init(), FB_SIZE_KB, get_fb_base_kb(), KiB, set_cpu_id(), and tps65090_thru_ec_fet_disable().
Definition at line 131 of file cpu.c.
References DIV_ROUND_UP, FB_SIZE_KB, get_fb_base_kb(), KiB, mmio_resource, RAM_BASE_KB, ram_resource, and RAM_SIZE_KB.
Definition at line 153 of file cpu.c.
References cpu_ops, and device::ops.
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Definition at line 55 of file cpu.c.
References ALIGN_DOWN, ALIGN_UP, BIOS_SPEW, device::chip_info, exynos5_fimd_panel::clkval_f, soc_samsung_exynos5420_config::clkval_f, dcache_clean_invalidate_by_mva, DCACHE_OFF, exynos5_fimd_panel::fixvclk, exynos5_fimd_panel::hsync, soc_samsung_exynos5420_config::hsync, exynos5_fimd_panel::is_dp, exynos5_fimd_panel::is_mipi, exynos5_fimd_panel::ivclk, exynos5_fimd_panel::left_margin, soc_samsung_exynos5420_config::left_margin, exynos5_fimd_panel::lower_margin, soc_samsung_exynos5420_config::lower_margin, memset(), MiB, mmu_config_range(), printk, exynos5_fimd_panel::right_margin, soc_samsung_exynos5420_config::right_margin, exynos5_fimd_panel::upper_margin, soc_samsung_exynos5420_config::upper_margin, exynos5_fimd_panel::vsync, soc_samsung_exynos5420_config::vsync, exynos5_fimd_panel::xres, soc_samsung_exynos5420_config::xres, exynos5_fimd_panel::yres, and soc_samsung_exynos5420_config::yres.
Referenced by cpu_enable().
Definition at line 19 of file cpu.c.
References cpu_id, cpu_rev, EXYNOS5_PRO_ID, and read32().
Referenced by cpu_enable().
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Definition at line 102 of file cpu.c.
References BIOS_ERR, google_chromeec_i2c_xfer(), printk, and value.
Referenced by cpu_enable().
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Definition at line 16 of file cpu.c.
Referenced by cpu_init(), and set_cpu_id().
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Definition at line 140 of file cpu.c.
Referenced by enable_exynos5420_dev().
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Definition at line 17 of file cpu.c.
Referenced by set_cpu_id().
struct chip_operations soc_samsung_exynos5420_ops |