coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
chip.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <acpi/acpi_device.h>
4 
14 };
15 
25 };
26 
32 };
33 
34 /*
35  * Cirrus Logic CS42L42 Audio Codec devicetree bindings
36  * linux/Documentation/devicetree/bindings/sound/cs42l42.txt
37  */
39  /* Interrupt configuration */
40  struct acpi_irq irq;
41 
42  /* Use GPIO based interrupt instead of PIRQ */
43  struct acpi_gpio irq_gpio;
44 
45  /* Use GPIO based reset gpio */
46  struct acpi_gpio reset_gpio;
47 
48  /* I2C Bus Frequency in Hertz (default 400kHz) */
49  unsigned int bus_speed;
50 
51  /* Define cs42L42 parameters */
52  /*
53  * cirrus,ts-inv : Boolean property. For jacks that invert the tip sense
54  * polarity. Normal jacks will short tip sense pin to HS1 when headphones are
55  * plugged in and leave tip sense floating when not plugged in. Inverting jacks
56  * short tip sense when unplugged and float when plugged in.
57  * false = Non-inverted
58  * true = Inverted
59  * Default = Non-inverted
60  */
61  bool ts_inv;
62  /*
63  * cirrus,ts-dbnc-rise : Debounce the rising edge of TIP_SENSE_PLUG. With no
64  * debounce, the tip sense pin might be noisy on a plug event.
65  * Default = RISE_DEB_1000_MS
66  */
68  /*
69  * cirrus,ts-dbnc-fall : Debounce the falling edge of TIP_SENSE_UNPLUG.
70  * With no debounce, the tip sense pin might be noisy on an unplug event.
71  * Default = FALL_DEB_1000_MS
72  */
74  /*
75  * cirrus,btn-det-init-dbnce : This sets how long the driver sleeps after
76  * enabling button detection interrupts. After auto-detection and before
77  * servicing button interrupts, the HS bias needs time to settle. If you
78  * don't wait, there is possibility for erroneous button interrupt.
79  * Value in ms, 0 - 200.
80  * Default = 100ms
81  */
82  unsigned int btn_det_init_dbnce;
83  /*
84  * cirrus,btn-det-event-dbnce : This sets how long the driver delays after
85  * receiving a button press interrupt. With level detect interrupts, you want
86  * to wait a small amount of time to make sure the button press is making a
87  * clean connection with the bias resistors.
88  * Value in ms, 0 - 20.
89  * Default = 10ms
90  */
91  unsigned int btn_det_event_dbnce;
92  /*
93  * cirrus,bias-lvls : For a level-detect headset button scheme, each button
94  * will bias the mic pin to a certain voltage. To determine which button was
95  * pressed, the driver will compare this biased voltage to sequential,
96  * decreasing voltages and will stop when a comparator is tripped,
97  * indicating a comparator voltage < bias voltage. This value represents a
98  * percentage of the internally generated HS bias voltage. For different
99  * hardware setups, a designer might want to tweak this. This is an array of
100  * descending values for the comparator voltage.
101  * Array of 4 values
102  * Each 0-63
103  * < x1 x2 x3 x4 >
104  * Default = < 15 8 4 1>
105  */
107  /* headset bias ramp rate */
109  /*
110  * cirrus,hs-bias-sense-disable: This is boolean property. If present the
111  * HSBIAS sense is disabled. Configures HSBIAS output current sense through
112  * the external 2.21-k resistor. HSBIAS_SENSE is hardware feature to reduce
113  * the potential pop noise during the headset plug out slowly. But on some
114  * platforms ESD voltage will affect it causing test to fail, especially
115  * with CTIA headset type. For different hardware setups, a designer might
116  * want to tweak default behavior.
117  */
119 };
cs42l42_ts_dbnc_rise
Definition: chip.h:5
@ RISE_DEB_1500_MS
Definition: chip.h:13
@ RISE_DEB_1250_MS
Definition: chip.h:12
@ RISE_DEB_750_MS
Definition: chip.h:10
@ RISE_DEB_1000_MS
Definition: chip.h:11
@ RISE_DEB_125_MS
Definition: chip.h:7
@ RISE_DEB_250_MS
Definition: chip.h:8
@ RISE_DEB_500_MS
Definition: chip.h:9
@ RISE_DEB_0_MS
Definition: chip.h:6
cs42l42_ts_dbnc_fall
Definition: chip.h:16
@ FALL_DEB_1000_MS
Definition: chip.h:22
@ FALL_DEB_0_MS
Definition: chip.h:17
@ FALL_DEB_125_MS
Definition: chip.h:18
@ FALL_DEB_500_MS
Definition: chip.h:20
@ FALL_DEB_1250_MS
Definition: chip.h:23
@ FALL_DEB_250_MS
Definition: chip.h:19
@ FALL_DEB_1500_MS
Definition: chip.h:24
@ FALL_DEB_750_MS
Definition: chip.h:21
cs42l42_hs_bias_ramp_rate
Definition: chip.h:27
@ HSBIAS_RAMP_FAST
Definition: chip.h:29
@ HSBIAS_RAMP_FAST_RISE_SLOW_FALL
Definition: chip.h:28
@ HSBIAS_RAMP_SLOWEST
Definition: chip.h:31
@ HSBIAS_RAMP_SLOW
Definition: chip.h:30
unsigned long long uint64_t
Definition: stdint.h:17
enum cs42l42_ts_dbnc_rise ts_dbnc_rise
Definition: chip.h:67
struct acpi_irq irq
Definition: chip.h:40
unsigned int bus_speed
Definition: chip.h:49
enum cs42l42_hs_bias_ramp_rate hs_bias_ramp_rate
Definition: chip.h:108
enum cs42l42_ts_dbnc_fall ts_dbnc_fall
Definition: chip.h:73
unsigned int btn_det_init_dbnce
Definition: chip.h:82
struct acpi_gpio reset_gpio
Definition: chip.h:46
struct acpi_gpio irq_gpio
Definition: chip.h:43
uint64_t bias_lvls[4]
Definition: chip.h:106
unsigned int btn_det_event_dbnce
Definition: chip.h:91