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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <acpi/acpi.h>
#include <ec/google/chromeec/ec.h>
#include <drivers/intel/gma/opregion.h>
#include <baseboard/variants.h>
#include <gpio.h>
#include <variant/sku.h>
#include <soc/intel/apollolake/chip.h>
Go to the source code of this file.
Functions | |
const char * | mainboard_vbt_filename (void) |
void | variant_smi_sleep (u8 slp_typ) |
void | variant_update_devtree (struct device *dev) |
const char* mainboard_vbt_filename | ( | void | ) |
Definition at line 11 of file variant.c.
References google_chromeec_get_board_sku(), SKU_19_HDMI_TS, SKU_49_2A2C_TS, SKU_50_HDMI, SKU_51_2A2C, SKU_52_HDMI_TS, SKU_9_HDMI, and sku_id().
Definition at line 32 of file variant.c.
References ACPI_S5, google_chromeec_get_board_sku(), power_off_lte_module(), SKU_17_LTE, SKU_18_LTE_TS, and SKU_39_1A2C_360_LTE_TS_NO_STYLUES.
Definition at line 50 of file variant.c.
References device::chip_info, soc_intel_apollolake_config::disable_xhci_lfps_pm, google_chromeec_get_board_sku(), NULL, SKU_17_LTE, SKU_18_LTE_TS, and SKU_39_1A2C_360_LTE_TS_NO_STYLUES.