#include <chip.h>

Collaboration diagram for southbridge_intel_i82801gx_config:

Data Fields
uint8_t	pirqa_routing
	Interrupt Routing configuration If bit7 is 1, the interrupt is disabled. More...

uint8_t	pirqb_routing

uint8_t	pirqc_routing

uint8_t	pirqd_routing

uint8_t	pirqe_routing

uint8_t	pirqf_routing

uint8_t	pirqg_routing

uint8_t	pirqh_routing

uint8_t	gpi0_routing
	GPI Routing configuration. More...

uint8_t	gpi1_routing

uint8_t	gpi2_routing

uint8_t	gpi3_routing

uint8_t	gpi4_routing

uint8_t	gpi5_routing

uint8_t	gpi6_routing

uint8_t	gpi7_routing

uint8_t	gpi8_routing

uint8_t	gpi9_routing

uint8_t	gpi10_routing

uint8_t	gpi11_routing

uint8_t	gpi12_routing

uint8_t	gpi13_routing

uint8_t	gpi14_routing

uint8_t	gpi15_routing

uint32_t	gpe0_en

uint16_t	alt_gp_smi_en

uint32_t	ide_enable_primary

uint32_t	ide_enable_secondary

enum sata_mode	sata_mode

uint32_t	sata_ports_implemented

bool	pcie_port_coalesce

int	c4onc3_enable:1

int	docking_supported:1

int	p_cnt_throttling_supported:1

int	c3_latency

uint32_t	gen1_dec

uint32_t	gen2_dec

uint32_t	gen3_dec

uint32_t	gen4_dec

Detailed Description

Definition at line 14 of file chip.h.

Field Documentation

◆ alt_gp_smi_en

uint16_t southbridge_intel_i82801gx_config::alt_gp_smi_en

Definition at line 55 of file chip.h.

◆ c3_latency

int southbridge_intel_i82801gx_config::c3_latency

Definition at line 69 of file chip.h.

◆ c4onc3_enable

int southbridge_intel_i82801gx_config::c4onc3_enable

Definition at line 66 of file chip.h.

◆ docking_supported

int southbridge_intel_i82801gx_config::docking_supported

Definition at line 67 of file chip.h.

◆ gen1_dec

uint32_t southbridge_intel_i82801gx_config::gen1_dec

Definition at line 72 of file chip.h.

◆ gen2_dec

uint32_t southbridge_intel_i82801gx_config::gen2_dec

Definition at line 73 of file chip.h.

◆ gen3_dec

uint32_t southbridge_intel_i82801gx_config::gen3_dec

Definition at line 74 of file chip.h.

◆ gen4_dec

uint32_t southbridge_intel_i82801gx_config::gen4_dec

Definition at line 75 of file chip.h.

◆ gpe0_en

uint32_t southbridge_intel_i82801gx_config::gpe0_en

Definition at line 54 of file chip.h.

◆ gpi0_routing

uint8_t southbridge_intel_i82801gx_config::gpi0_routing

GPI Routing configuration.

Only the lower two bits have a meaning: 00: No effect 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 10: SCI (if corresponding GPIO_EN bit is also set) 11: reserved

Definition at line 37 of file chip.h.

◆ gpi10_routing

uint8_t southbridge_intel_i82801gx_config::gpi10_routing

Definition at line 47 of file chip.h.

◆ gpi11_routing

uint8_t southbridge_intel_i82801gx_config::gpi11_routing

Definition at line 48 of file chip.h.

◆ gpi12_routing

uint8_t southbridge_intel_i82801gx_config::gpi12_routing

Definition at line 49 of file chip.h.

◆ gpi13_routing

uint8_t southbridge_intel_i82801gx_config::gpi13_routing

Definition at line 50 of file chip.h.

◆ gpi14_routing

uint8_t southbridge_intel_i82801gx_config::gpi14_routing

Definition at line 51 of file chip.h.

◆ gpi15_routing

uint8_t southbridge_intel_i82801gx_config::gpi15_routing

Definition at line 52 of file chip.h.

◆ gpi1_routing

uint8_t southbridge_intel_i82801gx_config::gpi1_routing

Definition at line 38 of file chip.h.

◆ gpi2_routing

uint8_t southbridge_intel_i82801gx_config::gpi2_routing

Definition at line 39 of file chip.h.

◆ gpi3_routing

uint8_t southbridge_intel_i82801gx_config::gpi3_routing

Definition at line 40 of file chip.h.

◆ gpi4_routing

uint8_t southbridge_intel_i82801gx_config::gpi4_routing

Definition at line 41 of file chip.h.

◆ gpi5_routing

uint8_t southbridge_intel_i82801gx_config::gpi5_routing

Definition at line 42 of file chip.h.

◆ gpi6_routing

uint8_t southbridge_intel_i82801gx_config::gpi6_routing

Definition at line 43 of file chip.h.

◆ gpi7_routing

uint8_t southbridge_intel_i82801gx_config::gpi7_routing

Definition at line 44 of file chip.h.

◆ gpi8_routing

uint8_t southbridge_intel_i82801gx_config::gpi8_routing

Definition at line 45 of file chip.h.

◆ gpi9_routing

uint8_t southbridge_intel_i82801gx_config::gpi9_routing

Definition at line 46 of file chip.h.

◆ ide_enable_primary

uint32_t southbridge_intel_i82801gx_config::ide_enable_primary

Definition at line 58 of file chip.h.

◆ ide_enable_secondary

uint32_t southbridge_intel_i82801gx_config::ide_enable_secondary

Definition at line 59 of file chip.h.

◆ p_cnt_throttling_supported

int southbridge_intel_i82801gx_config::p_cnt_throttling_supported

Definition at line 68 of file chip.h.

◆ pcie_port_coalesce

bool southbridge_intel_i82801gx_config::pcie_port_coalesce

Definition at line 64 of file chip.h.

◆ pirqa_routing

uint8_t southbridge_intel_i82801gx_config::pirqa_routing

Interrupt Routing configuration If bit7 is 1, the interrupt is disabled.

Definition at line 19 of file chip.h.

◆ pirqb_routing

uint8_t southbridge_intel_i82801gx_config::pirqb_routing

Definition at line 20 of file chip.h.

◆ pirqc_routing

uint8_t southbridge_intel_i82801gx_config::pirqc_routing

Definition at line 21 of file chip.h.

◆ pirqd_routing

uint8_t southbridge_intel_i82801gx_config::pirqd_routing

Definition at line 22 of file chip.h.

◆ pirqe_routing

uint8_t southbridge_intel_i82801gx_config::pirqe_routing

Definition at line 23 of file chip.h.

◆ pirqf_routing

uint8_t southbridge_intel_i82801gx_config::pirqf_routing

Definition at line 24 of file chip.h.

◆ pirqg_routing

uint8_t southbridge_intel_i82801gx_config::pirqg_routing

Definition at line 25 of file chip.h.

◆ pirqh_routing

uint8_t southbridge_intel_i82801gx_config::pirqh_routing

Definition at line 26 of file chip.h.

◆ sata_mode

enum sata_mode southbridge_intel_i82801gx_config::sata_mode