coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
pcie_rp.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
4 #define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
5 
6 #include <stdint.h>
7 
8 /*
9  * In schematic PCIe root port numbers are 1-based, but FSP use 0-based indexes for
10  * the configuration arrays and so this macro subtracts 1 to convert RP# to array index.
11  */
12 #define PCIE_RP(x) ((x) - 1)
13 #define PCH_RP(x) PCIE_RP(x)
14 #define CPU_RP(x) PCIE_RP(x)
15 
17  PCIE_RP_HOTPLUG = (1 << 0),
18  PCIE_RP_LTR = (1 << 1),
19  /* PCIE RP Advanced Error Report */
20  PCIE_RP_AER = (1 << 2),
21  /* Clock source is not used by the root port. */
23  /*
24  * Clock request signal requires probing before enabling CLKREQ# based power
25  * management.
26  */
28  /* Clock request signal is not used by the root port. */
30 };
31 
34  PCIE_CLK_LAN = (1 << 1),
35 };
36 
37 /* This enum is for passing into an FSP UPD, typically PcieRpL1Substates */
43 };
44 
45 /* This enum is for passing into an FSP UPD, typically ASPM */
53 };
54 
55 /* PCIe Root Ports */
57  /* CLKOUT_PCIE_P/N# used by this root port as per schematics. */
59  /* SRCCLKREQ# used by this root port as per schematics. */
61  enum pcie_rp_flags flags;
62  /* PCIe RP L1 substate */
64  /* PCIe RP ASPM */
66 };
67 
68 /*
69  * The PCIe Root Ports usually come in groups of up to 8 PCI-device
70  * functions.
71  *
72  * `slot` is the PCI device/slot number of such a group.
73  * `start` is the initial PCI function number within the group. This is useful
74  * in case the root port numbers are not contiguous within the slot.
75  * `count` is the number of functions within the group starting with the `start`
76  * function number.
77  * `lcap_port_base` is the starting index of physical port as described in LCAP
78  * register in PCIe config space. coreboot always uses 0 based indexing while
79  * referring to the PCIe port but LCAP registers uses 1-based indexing in
80  * most of the cases. Remapping logic needs to correctly map LCAP port number
81  * (1-based or n-based) to coreboot indexing (0-based).
82  */
83 struct pcie_rp_group {
84  unsigned int slot;
85  unsigned int start;
86  unsigned int count;
87  unsigned int lcap_port_base;
88 };
89 
90 static inline unsigned int rp_start_fn(const struct pcie_rp_group *group)
91 {
92  return group->start;
93 }
94 
95 static inline unsigned int rp_end_fn(const struct pcie_rp_group *group)
96 {
97  return group->start + group->count - 1;
98 }
99 
100 /*
101  * Update PCI paths of the root ports in the devicetree.
102  *
103  * Depending on the board layout and physical presence of downstream
104  * devices, individual root-port functions can be hidden and reordered.
105  * If we have device nodes for root ports in the static `devicetree.cb`,
106  * we need to update their PCI paths, so the nodes still control the
107  * correct root port. Device nodes for disabled root ports will be
108  * unlinked from the bus, to not interfere with PCI enumeration.
109  *
110  * Call this once, after root ports have been reordered, but before PCI
111  * enumeration.
112  *
113  * `groups` points to a list of groups terminated by an entry with `count == 0`.
114  * It is assumed that the first group includes the RPs 1 to the first group's
115  * `count` and that adjacent groups follow without gaps in the numbering.
116  */
117 void pcie_rp_update_devicetree(const struct pcie_rp_group *groups);
118 
119 /*
120  * Return mask of PCIe root ports that are enabled by mainboard. Mask is set in
121  * the same order as the root ports in pcie_rp_group groups table.
122  *
123  * Thus, the status of first root port in the groups table is indicated by bit 0
124  * in the returned mask, second root port by bit 1 and so on.
125 
126  * 1 in the bit position indicates root port is enabled, whereas 0 indicates root
127  * port is disabled. This function assumes that the maximum count of root ports
128  * in the groups table is <= 32.
129  */
130 uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);
131 
132 /* Get PCH root port groups */
133 const struct pcie_rp_group *soc_get_pch_rp_groups(void);
134 
139 };
140 
141 /* For PCIe RTD3 support, each SoC that uses it must implement this function. */
142 struct device; /* Not necessary to include all of device/device.h */
143 enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev);
144 
145 /* Return the virtual wire index that represents CPU-side PCIe root ports */
146 int soc_get_cpu_rp_vw_idx(const struct device *dev);
147 
148 #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */
pcie_rp_type
Definition: pcie_rp.h:135
@ PCIE_RP_PCH
Definition: pcie_rp.h:138
@ PCIE_RP_UNKNOWN
Definition: pcie_rp.h:136
@ PCIE_RP_CPU
Definition: pcie_rp.h:137
pcie_clk_src_flags
Definition: pcie_rp.h:32
@ PCIE_CLK_FREE_RUNNING
Definition: pcie_rp.h:33
@ PCIE_CLK_LAN
Definition: pcie_rp.h:34
static unsigned int rp_start_fn(const struct pcie_rp_group *group)
Definition: pcie_rp.h:90
L1_substates_control
Definition: pcie_rp.h:38
@ L1_SS_FSP_DEFAULT
Definition: pcie_rp.h:39
@ L1_SS_L1_1
Definition: pcie_rp.h:41
@ L1_SS_L1_2
Definition: pcie_rp.h:42
@ L1_SS_DISABLED
Definition: pcie_rp.h:40
const struct pcie_rp_group * soc_get_pch_rp_groups(void)
Definition: pcie_rp.c:50
static unsigned int rp_end_fn(const struct pcie_rp_group *group)
Definition: pcie_rp.h:95
ASPM_control
Definition: pcie_rp.h:46
@ ASPM_DISABLE
Definition: pcie_rp.h:48
@ ASPM_DEFAULT
Definition: pcie_rp.h:47
@ ASPM_L0S_L1
Definition: pcie_rp.h:51
@ ASPM_L1
Definition: pcie_rp.h:50
@ ASPM_AUTO
Definition: pcie_rp.h:52
@ ASPM_L0S
Definition: pcie_rp.h:49
pcie_rp_flags
Definition: pcie_rp.h:16
@ PCIE_RP_AER
Definition: pcie_rp.h:20
@ PCIE_RP_CLK_REQ_DETECT
Definition: pcie_rp.h:27
@ PCIE_RP_CLK_SRC_UNUSED
Definition: pcie_rp.h:22
@ PCIE_RP_LTR
Definition: pcie_rp.h:18
@ PCIE_RP_HOTPLUG
Definition: pcie_rp.h:17
@ PCIE_RP_CLK_REQ_UNUSED
Definition: pcie_rp.h:29
void pcie_rp_update_devicetree(const struct pcie_rp_group *groups)
Definition: pcie_rp.c:131
enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
Definition: pcie_rp.c:102
uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups)
Definition: pcie_helpers.c:24
int soc_get_cpu_rp_vw_idx(const struct device *dev)
Definition: pcie_rp.c:113
unsigned int uint32_t
Definition: stdint.h:14
unsigned char uint8_t
Definition: stdint.h:8
Definition: device.h:107
enum pcie_rp_flags flags
Definition: pcie_rp.h:61
enum L1_substates_control PcieRpL1Substates
Definition: pcie_rp.h:63
enum ASPM_control pcie_rp_aspm
Definition: pcie_rp.h:65
uint8_t clk_src
Definition: pcie_rp.h:58
uint8_t clk_req
Definition: pcie_rp.h:60
unsigned int start
Definition: pcie_rp.h:85
unsigned int count
Definition: pcie_rp.h:86
unsigned int lcap_port_base
Definition: pcie_rp.h:87
unsigned int slot
Definition: pcie_rp.h:84