coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <bootblock_common.h>
4 #include <device/mmio.h>
5 #include <gpio.h>
6 #include <soc/spi.h>
7 
8 #include "gpio.h"
9 
10 static void usb3_hub_reset(void)
11 {
13 }
14 
16 {
17  mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
18  mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
23 }
#define MHz
Definition: helpers.h:80
void setup_chromeos_gpios(void)
Definition: chromeos.c:10
void gpio_output(gpio_t gpio, int value)
Definition: gpio.c:194
__weak void bootblock_mainboard_init(void)
Definition: bootblock.c:19
static void usb3_hub_reset(void)
Definition: bootblock.c:10
#define GPIO_GSC_AP_INT_ODL
Definition: gpio.h:17
#define GPIO_USB3_HUB_RST_L
Definition: gpio.h:25
@ IRQ_TYPE_EDGE_RISING
Definition: gpio_common.h:55
void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type)
Definition: gpio.c:142
@ SPI_NOR_GPIO_SET1
Definition: spi.h:30
void mtk_snfc_init(int gpio_set)
Definition: spi.c:141
@ SPI_PAD0_MASK
Definition: spi_common.h:46
void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, unsigned int speed_hz, unsigned int tick_dly)
Definition: spi.c:56