coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
bootblock_common.h
>
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#include <
device/mmio.h
>
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#include <
gpio.h
>
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#include <soc/spi.h>
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#include "
gpio.h
"
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static
void
usb3_hub_reset
(
void
)
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{
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gpio_output
(
GPIO_USB3_HUB_RST_L
, 1);
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}
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void
bootblock_mainboard_init
(
void
)
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{
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mtk_spi_init
(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS,
SPI_PAD0_MASK
, 3 *
MHz
, 0);
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mtk_spi_init
(CONFIG_DRIVER_TPM_SPI_BUS,
SPI_PAD0_MASK
, 1 *
MHz
, 0);
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mtk_snfc_init
(
SPI_NOR_GPIO_SET1
);
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setup_chromeos_gpios
();
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gpio_eint_configure
(
GPIO_GSC_AP_INT_ODL
,
IRQ_TYPE_EDGE_RISING
);
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usb3_hub_reset
();
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}
bootblock_common.h
MHz
#define MHz
Definition:
helpers.h:80
setup_chromeos_gpios
void setup_chromeos_gpios(void)
Definition:
chromeos.c:10
mmio.h
gpio_output
void gpio_output(gpio_t gpio, int value)
Definition:
gpio.c:194
bootblock_mainboard_init
__weak void bootblock_mainboard_init(void)
Definition:
bootblock.c:19
usb3_hub_reset
static void usb3_hub_reset(void)
Definition:
bootblock.c:10
GPIO_GSC_AP_INT_ODL
#define GPIO_GSC_AP_INT_ODL
Definition:
gpio.h:17
GPIO_USB3_HUB_RST_L
#define GPIO_USB3_HUB_RST_L
Definition:
gpio.h:25
IRQ_TYPE_EDGE_RISING
@ IRQ_TYPE_EDGE_RISING
Definition:
gpio_common.h:55
gpio_eint_configure
void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type)
Definition:
gpio.c:142
SPI_NOR_GPIO_SET1
@ SPI_NOR_GPIO_SET1
Definition:
spi.h:30
mtk_snfc_init
void mtk_snfc_init(int gpio_set)
Definition:
spi.c:141
gpio.h
SPI_PAD0_MASK
@ SPI_PAD0_MASK
Definition:
spi_common.h:46
mtk_spi_init
void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, unsigned int speed_hz, unsigned int tick_dly)
Definition:
spi.c:56
src
mainboard
google
corsola
bootblock.c
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