coreboot
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uart8250reg.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef UART8250REG_H
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#define UART8250REG_H
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#include <types.h>
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/* Data */
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#define UART8250_RBR 0x00
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#define UART8250_TBR 0x00
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/* Control */
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#define UART8250_IER 0x01
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#define UART8250_IER_MSI BIT(3)
/* Enable Modem status interrupt */
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#define UART8250_IER_RLSI BIT(2)
/* Enable receiver line status interrupt */
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#define UART8250_IER_THRI BIT(1)
/* Enable Transmitter holding register int. */
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#define UART8250_IER_RDI BIT(0)
/* Enable receiver data interrupt */
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#define UART8250_IIR 0x02
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#define UART8250_IIR_NO_INT 0x01
/* No interrupts pending */
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#define UART8250_IIR_ID 0x06
/* Mask for the interrupt ID */
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#define UART8250_IIR_MSI 0x00
/* Modem status interrupt */
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#define UART8250_IIR_THRI 0x02
/* Transmitter holding register empty */
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#define UART8250_IIR_RDI 0x04
/* Receiver data interrupt */
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#define UART8250_IIR_RLSI 0x06
/* Receiver line status interrupt */
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#define UART8250_FCR 0x02
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#define UART8250_FCR_FIFO_EN BIT(0)
/* Fifo enable */
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#define UART8250_FCR_CLEAR_RCVR BIT(1)
/* Clear the RCVR FIFO */
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#define UART8250_FCR_CLEAR_XMIT BIT(2)
/* Clear the XMIT FIFO */
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#define UART8250_FCR_DMA_SELECT BIT(3)
/* For DMA applications */
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#define UART8250_FCR_TRIGGER_MASK (3 << 6)
/* Mask for the FIFO trigger range */
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#define UART8250_FCR_TRIGGER_1 (0 << 6)
/* Mask for trigger set at 1 */
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#define UART8250_FCR_TRIGGER_4 (1 << 6)
/* Mask for trigger set at 4 */
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#define UART8250_FCR_TRIGGER_8 (2 << 6)
/* Mask for trigger set at 8 */
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#define UART8250_FCR_TRIGGER_14 (3 << 6)
/* Mask for trigger set at 14 */
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#define UART8250_LCR 0x03
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#define UART8250_LCR_WLS_MSK 0x03
/* character length select mask */
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#define UART8250_LCR_WLS_5 0x00
/* 5 bit character length */
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#define UART8250_LCR_WLS_6 0x01
/* 6 bit character length */
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#define UART8250_LCR_WLS_7 0x02
/* 7 bit character length */
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#define UART8250_LCR_WLS_8 0x03
/* 8 bit character length */
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#define UART8250_LCR_STB BIT(2)
/* Number of stop Bits, off = 1, on = 1.5 or 2) */
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#define UART8250_LCR_PEN BIT(3)
/* Parity enable */
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#define UART8250_LCR_EPS BIT(4)
/* Even Parity Select */
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#define UART8250_LCR_STKP BIT(5)
/* Stick Parity */
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#define UART8250_LCR_SBRK BIT(6)
/* Set Break */
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#define UART8250_LCR_DLAB BIT(7)
/* Divisor latch access bit */
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#define UART8250_MCR 0x04
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#define UART8250_MCR_DTR BIT(0)
/* DTR */
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#define UART8250_MCR_RTS BIT(1)
/* RTS */
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#define UART8250_MCR_OUT1 BIT(2)
/* Out 1 */
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#define UART8250_MCR_OUT2 BIT(3)
/* Out 2 */
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#define UART8250_MCR_LOOP BIT(4)
/* Enable loopback test mode */
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#define UART8250_MCR_DMA_EN 0x04
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#define UART8250_MCR_TX_DFR 0x08
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#define UART8250_DLL 0x00
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#define UART8250_DLM 0x01
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/* Status */
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#define UART8250_LSR 0x05
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#define UART8250_LSR_DR BIT(0)
/* Data ready */
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#define UART8250_LSR_OE BIT(1)
/* Overrun */
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#define UART8250_LSR_PE BIT(2)
/* Parity error */
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#define UART8250_LSR_FE BIT(3)
/* Framing error */
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#define UART8250_LSR_BI BIT(4)
/* Break */
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#define UART8250_LSR_THRE BIT(5)
/* Xmit holding register empty */
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#define UART8250_LSR_TEMT BIT(6)
/* Xmitter empty */
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#define UART8250_LSR_ERR BIT(7)
/* Error */
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#define UART8250_MSR 0x06
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#define UART8250_MSR_DCD BIT(7)
/* Data Carrier Detect */
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#define UART8250_MSR_RI BIT(6)
/* Ring Indicator */
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#define UART8250_MSR_DSR BIT(5)
/* Data Set Ready */
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#define UART8250_MSR_CTS BIT(4)
/* Clear to Send */
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#define UART8250_MSR_DDCD BIT(3)
/* Delta DCD */
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#define UART8250_MSR_TERI BIT(2)
/* Trailing edge ring indicator */
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#define UART8250_MSR_DDSR BIT(1)
/* Delta DSR */
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#define UART8250_MSR_DCTS BIT(0)
/* Delta CTS */
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#define UART8250_SCR 0x07
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#define UART8250_SPR 0x07
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#endif
/* UART8250REG_H */
src
drivers
uart
uart8250reg.h
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