coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <fsp/api.h>
4 #include <soc/romstage.h>
5 #include <spd_bin.h>
6 #include <string.h>
7 
8 static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
9 {
10  const u8 dq_map[2][12] = {
11  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
12  0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
13  { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
14  0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
15  memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0]));
16  memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1]));
17 }
18 
19 static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
20 {
21  const u8 dqs_map[2][8] = {
22  { 0, 1, 2, 3, 4, 5, 6, 7 },
23  { 1, 0, 2, 3, 4, 5, 6, 7 } };
24  memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0]));
25  memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1]));
26 }
27 
28 static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
29 {
30  const u16 RcompResistor[3] = { 121, 81, 100 };
31  memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
32 }
33 
34 static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
35 {
36  static const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
37  memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
38 }
39 
40 void mainboard_memory_init_params(FSPM_UPD *mupd)
41 {
42  FSP_M_CONFIG *mem_cfg;
43  mem_cfg = &mupd->FspmConfig;
44 
45  mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0,
46  &mem_cfg->DqByteMapCh1);
47  mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0,
48  &mem_cfg->DqsMapCpu2DramCh1);
49  mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
50  mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
51 
52  struct spd_block blk = {
53  .addr_map = { 0x50, 0x52, },
54  };
55 
56  mem_cfg->DqPinsInterleaved = 1;
57  mem_cfg->CaVrefConfig = 2;
58 
59  get_spd_smbus(&blk);
60  dump_spd_info(&blk);
61 
62  mem_cfg->MemorySpdDataLen = blk.len;
63  mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
64  mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
65 }
void * memcpy(void *dest, const void *src, size_t n)
Definition: memcpy.c:7
#define FSP_M_CONFIG
Definition: fsp_upd.h:8
void mainboard_memory_init_params(FSPM_UPD *mupd)
Definition: romstage.c:22
static const u8 dqs_map[][8]
Definition: memory.c:17
static const u8 dq_map[][12]
Definition: memory.c:9
static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
Definition: romstage.c:28
static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
Definition: romstage.c:8
static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
Definition: romstage.c:34
static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
Definition: romstage.c:19
void get_spd_smbus(struct spd_block *blk)
Definition: smbuslib.c:72
void dump_spd_info(struct spd_block *blk)
Definition: spd_bin.c:10
unsigned long uintptr_t
Definition: stdint.h:21
uint16_t u16
Definition: stdint.h:48
uint8_t u8
Definition: stdint.h:45
Definition: ddr4.c:86
u8 addr_map[CONFIG_DIMM_MAX]
Definition: spd_bin.h:39
u8 * spd_array[CONFIG_DIMM_MAX]
Definition: spd_bin.h:40
uint16_t len
Definition: ddr4.c:89