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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <chip.h>
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| struct soc_intel_common_config soc_intel_skylake_config::common_soc_config |
| struct vr_config soc_intel_skylake_config::domain_vr_config[NUM_VR_DOMAINS] |
| struct i915_gpu_controller_info soc_intel_skylake_config::gfx |
| enum skylake_i2c_voltage soc_intel_skylake_config::i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX] |
| struct i915_gpu_panel_config soc_intel_skylake_config::panel_cfg |
Definition at line 1 of file chip.h.
Referenced by graphics_soc_panel_init().
| enum { ... } soc_intel_skylake_config::PchHdaVcType |
| enum { ... } soc_intel_skylake_config::pcie_rp_aspm[CONFIG_MAX_ROOT_PORTS] |
| enum { ... } soc_intel_skylake_config::pcie_rp_l1substates[CONFIG_MAX_ROOT_PORTS] |
| u8 soc_intel_skylake_config::PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS] |
| u8 soc_intel_skylake_config::PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS] |
| u8 soc_intel_skylake_config::PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS] |
| u8 soc_intel_skylake_config::PcieRpClkSrcNumber[CONFIG_MAX_ROOT_PORTS] |
| u8 soc_intel_skylake_config::PcieRpEnable[CONFIG_MAX_ROOT_PORTS] |
| u8 soc_intel_skylake_config::PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS] |
| u8 soc_intel_skylake_config::PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS] |
| enum { ... } soc_intel_skylake_config::PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS] |
| enum { ... } soc_intel_skylake_config::Peg0MaxLinkWidth |
| enum { ... } soc_intel_skylake_config::Peg1MaxLinkWidth |
| enum { ... } soc_intel_skylake_config::Peg2MaxLinkWidth |
| enum { ... } soc_intel_skylake_config::PmConfigPwrCycDur |
| enum { ... } soc_intel_skylake_config::PmConfigSlpAMinAssert |
| enum { ... } soc_intel_skylake_config::PmConfigSlpS3MinAssert |
| enum { ... } soc_intel_skylake_config::PmConfigSlpS4MinAssert |
| enum { ... } soc_intel_skylake_config::PmConfigSlpSusMinAssert |
| struct soc_power_limits_config soc_intel_skylake_config::power_limits_config |
| enum { ... } soc_intel_skylake_config::PrimaryDisplay |
| enum { ... } soc_intel_skylake_config::SaGv |
| enum { ... } soc_intel_skylake_config::SataMode |
| u8 soc_intel_skylake_config::SerialIoDevMode[PchSerialIoIndexMax] |
| enum { ... } soc_intel_skylake_config::SerialIrqConfigStartFramePulse |
| enum serirq_mode soc_intel_skylake_config::serirq_mode |
| struct usb2_port_config soc_intel_skylake_config::usb2_ports[16] |
| struct usb3_port_config soc_intel_skylake_config::usb3_ports[10] |
1.9.1