coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
amdblocks/acpimmio.h
>
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#include <
amdblocks/acpimmio_legacy_gpio100.h
>
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#include <
bootblock_common.h
>
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#include <
console/console.h
>
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#include <
superio/smsc/lpc47n217/lpc47n217.h
>
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#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1)
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void
bootblock_mainboard_early_init
(
void
)
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{
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post_code
(0x30);
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post_code
(0x31);
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gpio_100_write8
(0x1, 0x98);
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/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
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pm_write8
(0xea, 0x1);
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lpc47n217_enable_serial
(
SERIAL_DEV
, CONFIG_TTYS0_BASE);
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}
acpimmio.h
pm_write8
static void pm_write8(uint8_t reg, uint8_t value)
Definition:
acpimmio.h:181
acpimmio_legacy_gpio100.h
gpio_100_write8
static void gpio_100_write8(uint8_t reg, uint8_t value)
Definition:
acpimmio_legacy_gpio100.h:28
bootblock_common.h
console.h
bootblock_mainboard_early_init
__weak void bootblock_mainboard_early_init(void)
Definition:
bootblock.c:16
lpc47n217.h
SERIAL_DEV
#define SERIAL_DEV
Definition:
bootblock.c:9
post_code
#define post_code(value)
Definition:
post_code.h:12
lpc47n217_enable_serial
void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase)
Configure the base I/O port of the specified serial device and enable the serial device.
Definition:
early_serial.c:95
src
mainboard
amd
thatcher
bootblock.c
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