4 #ifndef AMD_COMMON_PSP_EFS_H
5 #define AMD_COMMON_PSP_EFS_H
9 #define EFS_OFFSET (0xffffff - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000 + 1)
11 #define EMBEDDED_FW_SIGNATURE 0x55aa55aa
13 #if CONFIG(SOC_AMD_STONEYRIDGE)
14 #define SPI_MODE_FIELD spi_readmode_f15_mod_60_6f
15 #define SPI_SPEED_FIELD fast_speed_new_f15_mod_60_6f
16 #elif CONFIG(SOC_AMD_PICASSO)
17 #define SPI_MODE_FIELD spi_readmode_f17_mod_00_2f
18 #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_00_2f
19 #elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_SABRINA)
20 #define SPI_MODE_FIELD spi_readmode_f17_mod_30_3f
21 #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_30_3f
23 #error <Error: Unknown Processor>
30 } __attribute__((packed));
32 #define EFS_SECOND_GEN 0
65 } __attribute__((packed, aligned(16)));
bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed)
uint8_t spi_fastspeed_f17_mod_00_2f
uint8_t qpr_dummy_cycle_f17_mod_00_2f
uint32_t combo_psp_directory
uint8_t spi_readmode_f17_mod_00_2f
uint8_t fast_speed_new_f15_mod_60_6f
uint8_t spi_fastspeed_f17_mod_30_3f
uint8_t micron_detect_f17_mod_30_3f
uint8_t spi_readmode_f15_mod_60_6f
uint8_t spi_readmode_f17_mod_30_3f
uint32_t promontory_fw_ptr
struct second_gen_efs efs_gen
uint32_t lp_promontory_fw_ptr