coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
addressmap.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__
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#define __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__
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#define MAX_DRAM_ADDRESS 0x2000000000ULL
/* 128GB */
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/* Physical addressed with bit 47 set indicate I/O memory space. */
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/* ARM code entry vector */
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#define BOOTROM_OFFSET 0x100000
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/* Start of IO space */
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#define IO_SPACE_START 0x800000000000ULL
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#define IO_SPACE_SIZE 0x100000000000ULL
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/* L2C */
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#define L2C_PF_BAR0 0x87E080800000ULL
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#define L2C_TAD0_PF_BAR0 (0x87E050000000ULL + 0x10000)
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#define L2C_TAD0_INT_W1C (0x87E050000000ULL + 0x40000)
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#define L2C_CBC0_PF_BAR0 0x87E058000000ULL
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#define L2C_MCI0_PF_BAR0 0x87E05C000000ULL
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/* LMC */
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#define LMC0_PF_BAR0 0x87E088000000ULL
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#define LMC0_DDR_PLL_CTL0 0x258
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/* OCLA */
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/* IOB */
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#define IOBN0_PF_BAR0 0x87E0F0000000ULL
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#define MRML_PF_BAR0 0x87E0FC000000ULL
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/* SMMU */
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#define SMMU_PF_BAR0 0x830000000000ULL
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/* GTI */
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#define GTI_PF_BAR0 0x844000000000ULL
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/* PCC */
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#define ECAM_PF_BAR2 0x848000000000ULL
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#define ECAM0_DEVX_NSDIS 0x87e048070000ULL
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#define ECAM0_DEVX_SDIS 0x87e048060000ULL
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#define ECAM0_RSLX_NSDIS 0x87e048050000ULL
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#define ECAM0_RSLX_SDIS 0x87e048040000ULL
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/* CPT */
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/* SLI */
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/* RST */
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#define RST_PF_BAR0 (0x87E006000000ULL + 0x1600)
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#define RST_PP_AVAILABLE (RST_PF_BAR0 + 0x138ULL)
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#define RST_PP_RESET (RST_PF_BAR0 + 0x140ULL)
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#define RST_PP_PENDING (RST_PF_BAR0 + 0x148ULL)
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#define FUSF_PF_BAR0 0x87E004000000ULL
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#define MIO_FUS_PF_BAR0 0x87E003000000ULL
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#define MIO_BOOT_PF_BAR0 0x87E000000000ULL
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#define MIO_BOOT_AP_JUMP (MIO_BOOT_PF_BAR0 + 0xD0ULL)
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/* PTP */
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#define MIO_PTP_PF_BAR0 0x807000000000ULL
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/* GIC */
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/* NIC */
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/* LBK */
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#define GTI_PF_BAR0 0x844000000000ULL
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/* DAP */
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/* BCH */
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/* KEY */
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/* RNG */
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#define GSER0_PF_BAR0 (0x87E090000000ULL + (0 << 24))
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#define GSER1_PF_BAR0 (0x87E090000000ULL + (1 << 24))
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#define GSER2_PF_BAR0 (0x87E090000000ULL + (2 << 24))
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#define GSER3_PF_BAR0 (0x87E090000000ULL + (3 << 24))
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#define GSERx_PF_BAR0(x) \
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((((x) == 0) || ((x) == 1) || ((x) == 2) || ((x) == 3)) ? \
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(0x87E090000000ULL + ((x) << 24)) : 0)
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/* PEM */
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#define PEM_PEMX_PF_BAR0(x) (0x87e0c0000000ULL + 0x1000000ULL * (x))
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/* SATA */
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/* USB */
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/* UAA */
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#define UAA0_PF_BAR0 (0x87E028000000ULL + (0 << 24))
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#define UAA1_PF_BAR0 (0x87E028000000ULL + (1 << 24))
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#define UAA2_PF_BAR0 (0x87E028000000ULL + (2 << 24))
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#define UAA3_PF_BAR0 (0x87E028000000ULL + (3 << 24))
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#define UAAx_PF_BAR0(x) \
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((((x) == 0) || ((x) == 1) || ((x) == 2) || ((x) == 3)) ? \
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(0x87E028000000ULL + ((x) << 24)) : 0)
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#define CAVM_GICD_SETSPI_NSR 0x801000000040ULL
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#define CAVM_GICD_CLRSPI_NSR 0x801000000048ULL
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/* TWSI */
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#define MIO_TWS0_PF_BAR0 (0x87E0D0000000ULL + (0 << 24))
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#define MIO_TWS1_PF_BAR0 (0x87E0D0000000ULL + (1 << 24))
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#define MIO_TWSx_PF_BAR0(x) \
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((((x) == 0) || ((x) == 1)) ? (0x87E0D0000000ULL + ((x) << 24)) : 0)
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/* GPIO */
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#define GPIO_PF_BAR0 0x803000000000ULL
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/* SGPIO */
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#define SGP_PF_BAR0 0x803000000000ULL
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/* SMI */
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/* SPI */
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#define MPI_PF_BAR0 (0x804000000000ULL + 0x1000)
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/* PCM */
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/* PBUS */
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/* NDF */
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/* EMM */
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/* VRM */
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/* VRM BARs are spaced apart by 0x1000000 */
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#define VRM0_PF_BAR0 0x87E021000000ULL
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#endif
/* __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__ */
src
soc
cavium
cn81xx
include
soc
addressmap.h
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