coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | MAX_DRAM_ADDRESS 0x2000000000ULL /* 128GB */ |
#define | BOOTROM_OFFSET 0x100000 |
#define | IO_SPACE_START 0x800000000000ULL |
#define | IO_SPACE_SIZE 0x100000000000ULL |
#define | L2C_PF_BAR0 0x87E080800000ULL |
#define | L2C_TAD0_PF_BAR0 (0x87E050000000ULL + 0x10000) |
#define | L2C_TAD0_INT_W1C (0x87E050000000ULL + 0x40000) |
#define | L2C_CBC0_PF_BAR0 0x87E058000000ULL |
#define | L2C_MCI0_PF_BAR0 0x87E05C000000ULL |
#define | LMC0_PF_BAR0 0x87E088000000ULL |
#define | LMC0_DDR_PLL_CTL0 0x258 |
#define | IOBN0_PF_BAR0 0x87E0F0000000ULL |
#define | MRML_PF_BAR0 0x87E0FC000000ULL |
#define | SMMU_PF_BAR0 0x830000000000ULL |
#define | GTI_PF_BAR0 0x844000000000ULL |
#define | ECAM_PF_BAR2 0x848000000000ULL |
#define | ECAM0_DEVX_NSDIS 0x87e048070000ULL |
#define | ECAM0_DEVX_SDIS 0x87e048060000ULL |
#define | ECAM0_RSLX_NSDIS 0x87e048050000ULL |
#define | ECAM0_RSLX_SDIS 0x87e048040000ULL |
#define | RST_PF_BAR0 (0x87E006000000ULL + 0x1600) |
#define | RST_PP_AVAILABLE (RST_PF_BAR0 + 0x138ULL) |
#define | RST_PP_RESET (RST_PF_BAR0 + 0x140ULL) |
#define | RST_PP_PENDING (RST_PF_BAR0 + 0x148ULL) |
#define | FUSF_PF_BAR0 0x87E004000000ULL |
#define | MIO_FUS_PF_BAR0 0x87E003000000ULL |
#define | MIO_BOOT_PF_BAR0 0x87E000000000ULL |
#define | MIO_BOOT_AP_JUMP (MIO_BOOT_PF_BAR0 + 0xD0ULL) |
#define | MIO_PTP_PF_BAR0 0x807000000000ULL |
#define | GTI_PF_BAR0 0x844000000000ULL |
#define | GSER0_PF_BAR0 (0x87E090000000ULL + (0 << 24)) |
#define | GSER1_PF_BAR0 (0x87E090000000ULL + (1 << 24)) |
#define | GSER2_PF_BAR0 (0x87E090000000ULL + (2 << 24)) |
#define | GSER3_PF_BAR0 (0x87E090000000ULL + (3 << 24)) |
#define | GSERx_PF_BAR0(x) |
#define | PEM_PEMX_PF_BAR0(x) (0x87e0c0000000ULL + 0x1000000ULL * (x)) |
#define | UAA0_PF_BAR0 (0x87E028000000ULL + (0 << 24)) |
#define | UAA1_PF_BAR0 (0x87E028000000ULL + (1 << 24)) |
#define | UAA2_PF_BAR0 (0x87E028000000ULL + (2 << 24)) |
#define | UAA3_PF_BAR0 (0x87E028000000ULL + (3 << 24)) |
#define | UAAx_PF_BAR0(x) |
#define | CAVM_GICD_SETSPI_NSR 0x801000000040ULL |
#define | CAVM_GICD_CLRSPI_NSR 0x801000000048ULL |
#define | MIO_TWS0_PF_BAR0 (0x87E0D0000000ULL + (0 << 24)) |
#define | MIO_TWS1_PF_BAR0 (0x87E0D0000000ULL + (1 << 24)) |
#define | MIO_TWSx_PF_BAR0(x) ((((x) == 0) || ((x) == 1)) ? (0x87E0D0000000ULL + ((x) << 24)) : 0) |
#define | GPIO_PF_BAR0 0x803000000000ULL |
#define | SGP_PF_BAR0 0x803000000000ULL |
#define | MPI_PF_BAR0 (0x804000000000ULL + 0x1000) |
#define | VRM0_PF_BAR0 0x87E021000000ULL |
#define BOOTROM_OFFSET 0x100000 |
Definition at line 11 of file addressmap.h.
#define CAVM_GICD_CLRSPI_NSR 0x801000000048ULL |
Definition at line 99 of file addressmap.h.
#define CAVM_GICD_SETSPI_NSR 0x801000000040ULL |
Definition at line 98 of file addressmap.h.
#define ECAM0_DEVX_NSDIS 0x87e048070000ULL |
Definition at line 42 of file addressmap.h.
#define ECAM0_DEVX_SDIS 0x87e048060000ULL |
Definition at line 43 of file addressmap.h.
#define ECAM0_RSLX_NSDIS 0x87e048050000ULL |
Definition at line 44 of file addressmap.h.
#define ECAM0_RSLX_SDIS 0x87e048040000ULL |
Definition at line 45 of file addressmap.h.
#define ECAM_PF_BAR2 0x848000000000ULL |
Definition at line 41 of file addressmap.h.
#define FUSF_PF_BAR0 0x87E004000000ULL |
Definition at line 56 of file addressmap.h.
#define GPIO_PF_BAR0 0x803000000000ULL |
Definition at line 108 of file addressmap.h.
#define GSER0_PF_BAR0 (0x87E090000000ULL + (0 << 24)) |
Definition at line 75 of file addressmap.h.
#define GSER1_PF_BAR0 (0x87E090000000ULL + (1 << 24)) |
Definition at line 76 of file addressmap.h.
#define GSER2_PF_BAR0 (0x87E090000000ULL + (2 << 24)) |
Definition at line 77 of file addressmap.h.
#define GSER3_PF_BAR0 (0x87E090000000ULL + (3 << 24)) |
Definition at line 78 of file addressmap.h.
#define GSERx_PF_BAR0 | ( | x | ) |
Definition at line 79 of file addressmap.h.
#define GTI_PF_BAR0 0x844000000000ULL |
Definition at line 68 of file addressmap.h.
#define GTI_PF_BAR0 0x844000000000ULL |
Definition at line 68 of file addressmap.h.
#define IO_SPACE_SIZE 0x100000000000ULL |
Definition at line 15 of file addressmap.h.
#define IO_SPACE_START 0x800000000000ULL |
Definition at line 14 of file addressmap.h.
#define IOBN0_PF_BAR0 0x87E0F0000000ULL |
Definition at line 31 of file addressmap.h.
#define L2C_CBC0_PF_BAR0 0x87E058000000ULL |
Definition at line 21 of file addressmap.h.
#define L2C_MCI0_PF_BAR0 0x87E05C000000ULL |
Definition at line 22 of file addressmap.h.
#define L2C_PF_BAR0 0x87E080800000ULL |
Definition at line 18 of file addressmap.h.
#define L2C_TAD0_INT_W1C (0x87E050000000ULL + 0x40000) |
Definition at line 20 of file addressmap.h.
#define L2C_TAD0_PF_BAR0 (0x87E050000000ULL + 0x10000) |
Definition at line 19 of file addressmap.h.
#define LMC0_DDR_PLL_CTL0 0x258 |
Definition at line 26 of file addressmap.h.
#define LMC0_PF_BAR0 0x87E088000000ULL |
Definition at line 25 of file addressmap.h.
#define MAX_DRAM_ADDRESS 0x2000000000ULL /* 128GB */ |
Definition at line 6 of file addressmap.h.
#define MIO_BOOT_AP_JUMP (MIO_BOOT_PF_BAR0 + 0xD0ULL) |
Definition at line 59 of file addressmap.h.
#define MIO_BOOT_PF_BAR0 0x87E000000000ULL |
Definition at line 58 of file addressmap.h.
#define MIO_FUS_PF_BAR0 0x87E003000000ULL |
Definition at line 57 of file addressmap.h.
#define MIO_PTP_PF_BAR0 0x807000000000ULL |
Definition at line 62 of file addressmap.h.
#define MIO_TWS0_PF_BAR0 (0x87E0D0000000ULL + (0 << 24)) |
Definition at line 102 of file addressmap.h.
#define MIO_TWS1_PF_BAR0 (0x87E0D0000000ULL + (1 << 24)) |
Definition at line 103 of file addressmap.h.
Definition at line 104 of file addressmap.h.
#define MPI_PF_BAR0 (0x804000000000ULL + 0x1000) |
Definition at line 116 of file addressmap.h.
#define MRML_PF_BAR0 0x87E0FC000000ULL |
Definition at line 32 of file addressmap.h.
Definition at line 84 of file addressmap.h.
#define RST_PF_BAR0 (0x87E006000000ULL + 0x1600) |
Definition at line 51 of file addressmap.h.
#define RST_PP_AVAILABLE (RST_PF_BAR0 + 0x138ULL) |
Definition at line 52 of file addressmap.h.
#define RST_PP_PENDING (RST_PF_BAR0 + 0x148ULL) |
Definition at line 54 of file addressmap.h.
#define RST_PP_RESET (RST_PF_BAR0 + 0x140ULL) |
Definition at line 53 of file addressmap.h.
#define SGP_PF_BAR0 0x803000000000ULL |
Definition at line 111 of file addressmap.h.
#define SMMU_PF_BAR0 0x830000000000ULL |
Definition at line 35 of file addressmap.h.
#define UAA0_PF_BAR0 (0x87E028000000ULL + (0 << 24)) |
Definition at line 90 of file addressmap.h.
#define UAA1_PF_BAR0 (0x87E028000000ULL + (1 << 24)) |
Definition at line 91 of file addressmap.h.
#define UAA2_PF_BAR0 (0x87E028000000ULL + (2 << 24)) |
Definition at line 92 of file addressmap.h.
#define UAA3_PF_BAR0 (0x87E028000000ULL + (3 << 24)) |
Definition at line 93 of file addressmap.h.
#define UAAx_PF_BAR0 | ( | x | ) |
#define VRM0_PF_BAR0 0x87E021000000ULL |
Definition at line 125 of file addressmap.h.