coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <acpi/acpi.h>
#include <sar.h>
#include <baseboard/variants.h>
#include <gpio.h>
#include <ec/google/chromeec/ec.h>
#include <soc/intel/apollolake/chip.h>
Go to the source code of this file.
Enumerations | |
enum | { SKU_37_DROID = 37 , SKU_38_DROID = 38 , SKU_39_DROID = 39 , SKU_40_DROID = 40 } |
Functions | |
const char * | get_wifi_sar_cbfs_filename (void) |
void | variant_smi_sleep (u8 slp_typ) |
void | variant_update_devtree (struct device *dev) |
anonymous enum |
const char* get_wifi_sar_cbfs_filename | ( | void | ) |
Definition at line 17 of file variant.c.
References google_chromeec_get_board_sku(), sku_id(), and WIFI_SAR_CBFS_DEFAULT_FILENAME.
Definition at line 27 of file variant.c.
References ACPI_S5, google_chromeec_get_board_sku(), power_off_lte_module(), SKU_37_DROID, SKU_38_DROID, SKU_39_DROID, and SKU_40_DROID.
Definition at line 46 of file variant.c.
References device::chip_info, soc_intel_apollolake_config::disable_xhci_lfps_pm, google_chromeec_get_board_sku(), and NULL.