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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | CHAUSIE_EC_CMD 0x666 |
#define | CHAUSIE_EC_DATA 0x662 |
#define | EC_GPIO_3_ADDR 0xA3 |
#define | EC_GPIO_LOM_RESET_AUX (1 << 1) |
#define | EC_GPIO_7_ADDR 0xA7 |
#define | EC_GPIO_DT_PWREN (1 << 2) |
#define | EC_GPIO_WWAN_MODULE_RST (1 << 5) |
#define | EC_GPIO_8_ADDR 0xA8 |
#define | EC_GPIO_SMBUS0_EN (1 << 0) |
#define | EC_GPIO_A_ADDR 0xAA |
#define | EC_GPIO_WWAN_PWREN (1 << 3) |
#define | EC_GPIO_M2_SSD0_PWREN (1 << 6) |
#define | EC_GPIO_LOM_PWREN (1 << 7) |
#define | EC_GPIO_C_ADDR 0xAC |
#define | EC_GPIO_DT_N_WLAN_SW (1 << 1) |
#define | EC_GPIO_MP2_SEL (1 << 2) |
#define | EC_GPIO_WWAN_N_LOM_SW (1 << 3) |
Functions | |
static void | configure_ec_gpio (void) |
void | chausie_ec_init (void) |
Definition at line 54 of file ec.c.
References CHAUSIE_EC_CMD, CHAUSIE_EC_DATA, configure_ec_gpio(), and ec_set_ports().
Referenced by bootblock_mainboard_init().
Definition at line 29 of file ec.c.
References EC_GPIO_3_ADDR, EC_GPIO_7_ADDR, EC_GPIO_8_ADDR, EC_GPIO_A_ADDR, EC_GPIO_C_ADDR, EC_GPIO_DT_N_WLAN_SW, EC_GPIO_DT_PWREN, EC_GPIO_LOM_PWREN, EC_GPIO_LOM_RESET_AUX, EC_GPIO_M2_SSD0_PWREN, EC_GPIO_MP2_SEL, EC_GPIO_SMBUS0_EN, EC_GPIO_WWAN_MODULE_RST, EC_GPIO_WWAN_N_LOM_SW, EC_GPIO_WWAN_PWREN, ec_read(), and ec_write().
Referenced by chausie_ec_init().