coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio_defs.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _DENVERTON_NS_GPIO_DEFS_H_
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#define _DENVERTON_NS_GPIO_DEFS_H_
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#include <
soc/pcr.h
>
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/*
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* There are 3 GPIO groups. North Community, South Community DFX/Group0/Group1.
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* The GPIO groups are accessed through register blocks called communities.
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*/
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#define V_PCH_GPIO_NC_PAD_MAX 41
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#define V_PCH_GPIO_SC_DFX_PAD_MAX 18
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#define V_PCH_GPIO_SC0_PAD_MAX 53
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#define V_PCH_GPIO_SC1_PAD_MAX 42
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#define V_PCH_GPIO_GROUP_MAX 4
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//
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// GPIO Community 0 Private Configuration Registers
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//
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//
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// Power Group NORTH_ALL
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//
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#define R_PCH_PCR_GPIO_NC_PAD_OWN 0x20
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#define R_PCH_PCR_GPIO_NC_GPI_VWM_EN 0x70
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#define R_PCH_PCR_GPIO_NC_PADCFGLOCK 0x90
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#define R_PCH_PCR_GPIO_NC_PADCFGLOCKTX 0x94
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#define R_PCH_PCR_GPIO_NC1_PADCFGLOCK_1 0x98
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#define R_PCH_PCR_GPIO_NC1_PADCFGLOCKTX_1 0x9C
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#define R_PCH_PCR_GPIO_NC_HOSTSW_OWN 0xC0
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#define R_PCH_PCR_GPIO_NC_GPI_IS 0x0100
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#define R_PCH_PCR_GPIO_NC_GPI_IE 0x0120
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#define R_PCH_PCR_GPIO_NC_GPI_GPE_STS 0x0140
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#define R_PCH_PCR_GPIO_NC_GPI_GPE_EN 0x0160
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#define R_PCH_PCR_GPIO_NC_SMI_STS 0x0180
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#define R_PCH_PCR_GPIO_NC_SMI_EN 0x01A0
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#define R_PCH_PCR_GPIO_NC_NMI_STS 0x01C0
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#define R_PCH_PCR_GPIO_NC_NMI_EN 0x01E0
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#define R_PCH_PCR_GPIO_NC_PADCFG_OFFSET 0x400
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//
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// GPIO Community 1 Private Configuration Registers
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//
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//
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// Power Group SOUTH_DFX
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//
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#define R_PCH_PCR_GPIO_SC_DFX_PAD_OWN 0x20
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#define R_PCH_PCR_GPIO_SC_DFX_GPI_VWM_EN 0x70
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#define R_PCH_PCR_GPIO_SC_DFX_PADCFGLOCK 0x90
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#define R_PCH_PCR_GPIO_SC_DFX_PADCFGLOCKTX 0x94
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#define R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN 0xC0
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#define R_PCH_PCR_GPIO_SC_DFX_GPI_IS 0x0100
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#define R_PCH_PCR_GPIO_SC_DFX_GPI_IE 0x0120
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#define R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS 0x0140
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#define R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN 0x0160
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#define R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET 0x400
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//
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// Power Group SOUTH_GROUP0
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//
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#define R_PCH_PCR_GPIO_SC0_PAD_OWN 0x2C
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#define R_PCH_PCR_GPIO_SC0_GPI_VWM_EN 0x74
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#define R_PCH_PCR_GPIO_SC0_PADCFGLOCK 0x98
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#define R_PCH_PCR_GPIO_SC0_PADCFGLOCKTX 0x9C
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#define R_PCH_PCR_GPIO_SC0_HOSTSW_OWN 0xC4
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#define R_PCH_PCR_GPIO_SC0_GPI_IS 0x0104
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#define R_PCH_PCR_GPIO_SC0_GPI_IE 0x0124
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#define R_PCH_PCR_GPIO_SC0_GPI_GPE_STS 0x0144
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#define R_PCH_PCR_GPIO_SC0_GPI_GPE_EN 0x0164
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#define R_PCH_PCR_GPIO_SC0_SMI_STS 0x0184
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#define R_PCH_PCR_GPIO_SC0_SMI_EN 0x01A4
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#define R_PCH_PCR_GPIO_SC0_NMI_STS 0x01C4
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#define R_PCH_PCR_GPIO_SC0_NMI_EN 0x01E4
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#define R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET 0x490
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//
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// Power Group SOUTH_GROUP1
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//
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#define R_PCH_PCR_GPIO_SC1_PAD_OWN 0x48
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#define R_PCH_PCR_GPIO_SC1_GPI_VWM_EN 0x7C
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#define R_PCH_PCR_GPIO_SC1_PADCFGLOCK 0xA8
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#define R_PCH_PCR_GPIO_SC1_PADCFGLOCKTX 0xAC
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#define R_PCH_PCR_GPIO_SC1_HOSTSW_OWN 0xCC
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#define R_PCH_PCR_GPIO_SC1_GPI_IS 0x010C
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#define R_PCH_PCR_GPIO_SC1_GPI_IE 0x012C
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#define R_PCH_PCR_GPIO_SC1_GPI_GPE_STS 0x014C
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#define R_PCH_PCR_GPIO_SC1_GPI_GPE_EN 0x016C
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#define R_PCH_PCR_GPIO_SC1_SMI_STS 0x018C
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#define R_PCH_PCR_GPIO_SC1_SMI_EN 0x01AC
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#define R_PCH_PCR_GPIO_SC1_NMI_STS 0x01CC
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#define R_PCH_PCR_GPIO_SC1_NMI_EN 0x01EC
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#define R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET 0x638
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_NORTH_ALL_0 0x90
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_NORTH_ALL_0 0x94
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_NORTH_ALL_1 0x98
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_NORTH_ALL_1 0x9C
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_DFX_0 0x90
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_DFX_0 0x94
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP0_0 0x98
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP0_0 0x9C
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP0_1 0xA0
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP0_1 0xA4
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP1_0 0xA8
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP1_0 0xAC
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP1_1 0xB0
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#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP1_1 0xB4
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//
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// Pad Configuration Register DW0
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//
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// Pad Reset Config
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#define B_PCH_GPIO_RST_CONF ((1 << 31) | (1 << 30))
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#define N_PCH_GPIO_RST_CONF 30
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#define V_PCH_GPIO_RST_CONF_POW_GOOD 0x00
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#define V_PCH_GPIO_RST_CONF_DEEP_RST 0x01
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#define V_PCH_GPIO_RST_CONF_GPIO_RST 0x02
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#define V_PCH_GPIO_RST_CONF_RESUME_RST 0x03
// Only for GPD Group
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// RX Pad State Select
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#define B_PCH_GPIO_RX_PAD_STATE (1 << 29)
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#define N_PCH_GPIO_RX_PAD_STATE 29
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#define V_PCH_GPIO_RX_PAD_STATE_RAW 0x00
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#define V_PCH_GPIO_RX_PAD_STATE_INT 0x01
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// RX Raw Override to 1
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#define B_PCH_GPIO_RX_RAW1 (1 << 28)
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#define N_PCH_GPIO_RX_RAW1 28
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#define V_PCH_GPIO_RX_RAW1_DIS 0x00
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#define V_PCH_GPIO_RX_RAW1_EN 0x01
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// RX Level/Edge Configuration
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#define B_PCH_GPIO_RX_LVL_EDG ((1 << 26) | (1 << 25))
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#define N_PCH_GPIO_RX_LVL_EDG 25
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#define V_PCH_GPIO_RX_LVL_EDG_LVL 0x00
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#define V_PCH_GPIO_RX_LVL_EDG_EDG 0x01
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#define V_PCH_GPIO_RX_LVL_EDG_0 0x02
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#define V_PCH_GPIO_RX_LVL_EDG_RIS_FAL 0x03
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// RX Level/Edge Configuration
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#define B_PCH_GPIO_PRE_GFRX_SEL (1 << 24)
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#define N_PCH_GPIO_PRE_GFRX_SEL 24
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#define V_PCH_GPIO_PRE_GFRX_SEL_DIS 0x00
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#define V_PCH_GPIO_PRE_GFRX_SEL_EN 0x01
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// RX Invert
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#define B_PCH_GPIO_RXINV (1 << 23)
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#define N_PCH_GPIO_RXINV 23
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#define V_PCH_GPIO_RXINV_NO 0x00
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#define V_PCH_GPIO_RXINV_YES 0x01
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// RXTXENCFG
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#define B_PCH_GPIO_RXTXENCFG ((1 << 22) | (1 << 21))
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#define N_PCH_GPIO_RXTXENCFG 21
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#define V_PCH_GPIO_RXTXENCFG_DEF_FUN 0x00
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#define V_PCH_GPIO_RXTXENCFG_TX_EN_L 0x01
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#define V_PCH_GPIO_RXTXENCFG_TX_EN_H 0x02
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#define V_PCH_GPIO_RXTXENCFG_TXRXEN 0x03
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// GPIO Input Route IOxAPIC
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#define B_PCH_GPIO_RX_APIC_ROUTE (1 << 20)
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#define N_PCH_GPIO_RX_APIC_ROUTE 20
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#define V_PCH_GPIO_RX_APIC_ROUTE_DIS 0x00
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#define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01
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// GPIO Input Route SCI
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#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 19)
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#define N_PCH_GPIO_RX_SCI_ROUTE 19
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#define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00
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#define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01
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// GPIO Input Route SMI
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#define B_PCH_GPIO_RX_SMI_ROUTE (1 << 18)
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#define N_PCH_GPIO_RX_SMI_ROUTE 18
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#define V_PCH_GPIO_RX_SMI_ROUTE_DIS 0x00
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#define V_PCH_GPIO_RX_SMI_ROUTE_EN 0x01
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// GPIO Input Route NMI
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#define B_PCH_GPIO_RX_NMI_ROUTE (1 << 17)
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#define N_PCH_GPIO_RX_NMI_ROUTE 17
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#define V_PCH_GPIO_RX_NMI_ROUTE_DIS 0x00
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#define V_PCH_GPIO_RX_NMI_ROUTE_EN 0x01
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// GPIO Pad Mode
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#define B_PCH_GPIO_PAD_MODE ((1 << 12) | (1 << 11) | (1 << 10))
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#define N_PCH_GPIO_PAD_MODE 10
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#define V_PCH_GPIO_PAD_MODE_GPIO 0
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#define V_PCH_GPIO_PAD_MODE_NAT_1 1
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#define V_PCH_GPIO_PAD_MODE_NAT_2 2
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#define V_PCH_GPIO_PAD_MODE_NAT_3 3
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#define V_PCH_GPIO_PAD_MODE_NAT_4 4
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#define V_PCH_GPIO_PAD_MODE_NAT_5 5
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#define V_PCH_GPIO_PAD_MODE_NAT_6 6
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#define V_PCH_GPIO_PAD_MODE_NAT_7 7
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// GPIO RX Disable
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#define B_PCH_GPIO_RXDIS (1 << 9)
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#define N_PCH_GPIO_RXDIS 9
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#define V_PCH_GPIO_RXDIS_EN 0x00
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#define V_PCH_GPIO_RXDIS_DIS 0x01
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// GPIO TX Disable
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#define B_PCH_GPIO_TXDIS (1 << 8)
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#define N_PCH_GPIO_TXDIS 8
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#define V_PCH_GPIO_TXDIS_EN 0x00
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#define V_PCH_GPIO_TXDIS_DIS 0x01
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// GPIO RX State
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#define B_PCH_GPIO_RX_STATE (1 << 1)
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#define N_PCH_GPIO_RX_STATE 1
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#define V_PCH_GPIO_RX_STATE_LOW 0x00
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#define V_PCH_GPIO_RX_STATE_HIGH 0x01
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// GPIO TX State
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#define B_PCH_GPIO_TX_STATE (1 << 0)
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#define N_PCH_GPIO_TX_STATE 0
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#define V_PCH_GPIO_TX_STATE_LOW 0x00
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#define V_PCH_GPIO_TX_STATE_HIGH 0x01
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//
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// Pad Configuration Register DW1
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//
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// Padtol
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#define B_PCH_GPIO_PADTOL (1 << 25)
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#define N_PCH_GPIO_PADTOL 25
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#define V_PCH_GPIO_PADTOL_NONE 0x00
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#define V_PCH_GPIO_PADTOL_CLEAR 0x00
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#define V_PCH_GPIO_PADTOL_SET 0x01
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// Termination
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#define B_PCH_GPIO_TERM ((1 << 13) | (1 << 12) | (1 << 11) | (1 << 10))
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#define N_PCH_GPIO_TERM 10
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#define V_PCH_GPIO_TERM_WPD_NONE 0x00
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#define V_PCH_GPIO_TERM_WPD_5K 0x02
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#define V_PCH_GPIO_TERM_WPD_20K 0x04
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#define V_PCH_GPIO_TERM_WPU_NONE 0x08
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#define V_PCH_GPIO_TERM_WPU_1K 0x09
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#define V_PCH_GPIO_TERM_WPU_2K 0x0B
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#define V_PCH_GPIO_TERM_WPU_5K 0x0A
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#define V_PCH_GPIO_TERM_WPU_20K 0x0C
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#define V_PCH_GPIO_TERM_WPU_1K_2K 0x0D
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#define V_PCH_GPIO_TERM_NATIVE 0x0F
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#define PID_NorthCommunity PID_GPIOCOM0
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#define PID_SouthCommunity PID_GPIOCOM1
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// GPIO_MISC0
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// HSUART0: 101, 102, 13, 98
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// HSUART1: 96, 97,95 94
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#define GPIO_SMB3_CLTT_DATA 12
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#define R_PAD_CFG_DW0_SMB3_CLTT_DATA 0x490
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#define PID_SMB3_CLTT_DATA PID_SouthCommunity
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#define GPIO_SMB3_CLTT_CLK 13
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#define R_PAD_CFG_DW0_SMB3_CLTT_CLK 0x498
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#define PID_SMB3_CLTT_CLK PID_SouthCommunity
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#define GPIO_PCIE_CLKREQ5_N 98
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#define R_PAD_CFG_DW0_PCIE_CLKREQ5_N 0x4A0
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#define PID_PCIE_CLKREQ5_N PID_SouthCommunity
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#define GPIO_PCIE_CLKREQ6_N 99
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#define R_PAD_CFG_DW0_PCIE_CLKREQ6_N 0x4a8
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#define PID_PCIE_CLKREQ6_N PID_SouthCommunity
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#define GPIO_PCIE_CLKREQ7_N 100
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#define R_PAD_CFG_DW0_PCIE_CLKREQ7_N 0x4b0
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#define PID_PCIE_CLKREQ7_N PID_SouthCommunity
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#define GPIO_UART0_RXD 101
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#define R_PAD_CFG_DW0_UART0_RXD 0x4b8
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#define PID_UART0_RXD PID_SouthCommunity
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#define GPIO_UART0_TXD 102
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#define R_PAD_CFG_DW0_UART0_TXD 0x4c0
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#define PID_UART0_TXD PID_SouthCommunity
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#define GPIO_UART1_RXD 96
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#define R_PAD_CFG_DW0_UART1_RXD 0x5b8
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#define PID_UART1_RXD PID_SouthCommunity
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#define GPIO_UART1_TXD 97
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#define R_PAD_CFG_DW0_UART1_TXD 0x5c0
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#define PID_UART1_TXD PID_SouthCommunity
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#define GPIO_SATA1_SDOUT 95
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#define R_PAD_CFG_DW0_SATA1_SDOUT 0x5b0
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#define PID_SATA1_SDOUT PID_SouthCommunity
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#define GPIO_SATA0_SDOUT 94
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#define R_PAD_CFG_DW0_SATA0_SDOUT 0x5a8
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#define PID_SATA0_SDOUT PID_SouthCommunity
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///
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/// Denverton GPIO Groups
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///
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#define GPIO_DNV_GROUP_NC 0x0100
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#define GPIO_DNV_GROUP_SC_DFX 0x0101
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#define GPIO_DNV_GROUP_SC0 0x0102
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#define GPIO_DNV_GROUP_SC1 0x0103
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#define GPIO_DNV_GROUP_MIN GPIO_DNV_GROUP_NC
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#define GPIO_DNV_GROUP_MAX GPIO_DNV_GROUP_SC1
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#define NORTH_ALL_GBE0_SDP0 0x01000000
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#define NORTH_ALL_GBE1_SDP0 0x01000001
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#define NORTH_ALL_GBE0_SDP1 0x01000002
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#define NORTH_ALL_GBE1_SDP1 0x01000003
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#define NORTH_ALL_GBE0_SDP2 0x01000004
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#define NORTH_ALL_GBE1_SDP2 0x01000005
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#define NORTH_ALL_GBE0_SDP3 0x01000006
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#define NORTH_ALL_GBE1_SDP3 0x01000007
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#define NORTH_ALL_GBE2_LED0 0x01000008
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#define NORTH_ALL_GBE2_LED1 0x01000009
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#define NORTH_ALL_GBE0_I2C_CLK 0x0100000A
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#define NORTH_ALL_GBE0_I2C_DATA 0x0100000B
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#define NORTH_ALL_GBE1_I2C_CLK 0x0100000C
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#define NORTH_ALL_GBE1_I2C_DATA 0x0100000D
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#define NORTH_ALL_NCSI_RXD0 0x0100000E
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#define NORTH_ALL_NCSI_CLK_IN 0x0100000F
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#define NORTH_ALL_NCSI_RXD1 0x01000010
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#define NORTH_ALL_NCSI_CRS_DV 0x01000011
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#define NORTH_ALL_NCSI_ARB_IN 0x01000012
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#define NORTH_ALL_NCSI_TX_EN 0x01000013
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#define NORTH_ALL_NCSI_TXD0 0x01000014
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#define NORTH_ALL_NCSI_TXD1 0x01000015
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#define NORTH_ALL_NCSI_ARB_OUT 0x01000016
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#define NORTH_ALL_GBE0_LED0 0x01000017
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#define NORTH_ALL_GBE0_LED1 0x01000018
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#define NORTH_ALL_GBE1_LED0 0x01000019
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#define NORTH_ALL_GBE1_LED1 0x0100001A
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#define NORTH_ALL_GPIO_0 0x0100001B
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#define NORTH_ALL_PCIE_CLKREQ0_N 0x0100001C
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#define NORTH_ALL_PCIE_CLKREQ1_N 0x0100001D
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#define NORTH_ALL_PCIE_CLKREQ2_N 0x0100001E
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#define NORTH_ALL_PCIE_CLKREQ3_N 0x0100001F
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#define NORTH_ALL_PCIE_CLKREQ4_N 0x01000020
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#define NORTH_ALL_GPIO_1 0x01000021
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#define NORTH_ALL_GPIO_2 0x01000022
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#define NORTH_ALL_SVID_ALERT_N 0x01000023
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#define NORTH_ALL_SVID_DATA 0x01000024
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#define NORTH_ALL_SVID_CLK 0x01000025
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#define NORTH_ALL_THERMTRIP_N 0x01000026
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#define NORTH_ALL_PROCHOT_N 0x01000027
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#define NORTH_ALL_MEMHOT_N 0x01000028
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#define SOUTH_DFX_DFX_PORT_CLK0 0x01010000
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#define SOUTH_DFX_DFX_PORT_CLK1 0x01010001
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#define SOUTH_DFX_DFX_PORT0 0x01010002
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#define SOUTH_DFX_DFX_PORT1 0x01010003
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#define SOUTH_DFX_DFX_PORT2 0x01010004
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#define SOUTH_DFX_DFX_PORT3 0x01010005
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#define SOUTH_DFX_DFX_PORT4 0x01010006
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#define SOUTH_DFX_DFX_PORT5 0x01010007
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#define SOUTH_DFX_DFX_PORT6 0x01010008
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#define SOUTH_DFX_DFX_PORT7 0x01010009
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#define SOUTH_DFX_DFX_PORT8 0x0101000A
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#define SOUTH_DFX_DFX_PORT9 0x0101000B
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#define SOUTH_DFX_DFX_PORT10 0x0101000C
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#define SOUTH_DFX_DFX_PORT11 0x0101000D
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#define SOUTH_DFX_DFX_PORT12 0x0101000E
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#define SOUTH_DFX_DFX_PORT13 0x0101000F
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#define SOUTH_DFX_DFX_PORT14 0x01010010
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#define SOUTH_DFX_DFX_PORT15 0x01010011
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#define SOUTH_GROUP0_SMB3_CLTT_DATA 0x01020000
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#define SOUTH_GROUP0_SMB3_CLTT_CLK 0x01020001
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#define SOUTH_GROUP0_GPIO_12 0x01020000
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#define SOUTH_GROUP0_SMB5_GBE_ALRT_N 0x01020001
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#define SOUTH_GROUP0_PCIE_CLKREQ5_N 0x01020002
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#define SOUTH_GROUP0_PCIE_CLKREQ6_N 0x01020003
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#define SOUTH_GROUP0_PCIE_CLKREQ7_N 0x01020004
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#define SOUTH_GROUP0_UART0_RXD 0x01020005
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#define SOUTH_GROUP0_UART0_TXD 0x01020006
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#define SOUTH_GROUP0_SMB5_GBE_CLK 0x01020007
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#define SOUTH_GROUP0_SMB5_GBE_DATA 0x01020008
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#define SOUTH_GROUP0_ERROR2_N 0x01020009
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#define SOUTH_GROUP0_ERROR1_N 0x0102000A
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#define SOUTH_GROUP0_ERROR0_N 0x0102000B
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#define SOUTH_GROUP0_IERR_N 0x0102000C
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#define SOUTH_GROUP0_MCERR_N 0x0102000D
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#define SOUTH_GROUP0_SMB0_LEG_CLK 0x0102000E
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#define SOUTH_GROUP0_SMB0_LEG_DATA 0x0102000F
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#define SOUTH_GROUP0_SMB0_LEG_ALRT_N 0x01020010
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#define SOUTH_GROUP0_SMB1_HOST_DATA 0x01020011
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#define SOUTH_GROUP0_SMB1_HOST_CLK 0x01020012
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#define SOUTH_GROUP0_SMB2_PECI_DATA 0x01020013
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#define SOUTH_GROUP0_SMB2_PECI_CLK 0x01020014
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#define SOUTH_GROUP0_SMB4_CSME0_DATA 0x01020015
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#define SOUTH_GROUP0_SMB4_CSME0_CLK 0x01020016
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#define SOUTH_GROUP0_SMB4_CSME0_ALRT_N 0x01020017
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#define SOUTH_GROUP0_USB_OC0_N 0x01020018
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#define SOUTH_GROUP0_FLEX_CLK_SE0 0x01020019
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#define SOUTH_GROUP0_FLEX_CLK_SE1 0x0102001A
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#define SOUTH_GROUP0_GPIO_4 0x0102001B
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#define SOUTH_GROUP0_GPIO_5 0x0102001C
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#define SOUTH_GROUP0_GPIO_6 0x0102001D
400
#define SOUTH_GROUP0_GPIO_7 0x0102001E
401
#define SOUTH_GROUP0_SATA0_LED_N 0x0102001F
402
#define SOUTH_GROUP0_SATA1_LED_N 0x01020020
403
#define SOUTH_GROUP0_SATA_PDETECT0 0x01020021
404
#define SOUTH_GROUP0_SATA_PDETECT1 0x01020022
405
#define SOUTH_GROUP0_SATA0_SDOUT 0x01020023
406
#define SOUTH_GROUP0_SATA1_SDOUT 0x01020024
407
#define SOUTH_GROUP0_UART1_RXD 0x01020025
408
#define SOUTH_GROUP0_UART1_TXD 0x01020026
409
#define SOUTH_GROUP0_GPIO_8 0x01020027
410
#define SOUTH_GROUP0_GPIO_9 0x01020028
411
#define SOUTH_GROUP0_TCK 0x01020029
412
#define SOUTH_GROUP0_TRST_N 0x0102002A
413
#define SOUTH_GROUP0_TMS 0x0102002B
414
#define SOUTH_GROUP0_TDI 0x0102002C
415
#define SOUTH_GROUP0_TDO 0x0102002D
416
#define SOUTH_GROUP0_CX_PRDY_N 0x0102002E
417
#define SOUTH_GROUP0_CX_PREQ_N 0x0102002F
418
#define SOUTH_GROUP0_CTBTRIGINOUT 0x01020030
419
#define SOUTH_GROUP0_CTBTRIGOUT 0x01020031
420
#define SOUTH_GROUP0_DFX_SPARE2 0x01020032
421
#define SOUTH_GROUP0_DFX_SPARE3 0x01020033
422
#define SOUTH_GROUP0_DFX_SPARE4 0x01020034
423
#define SOUTH_GROUP1_SUSPWRDNACK 0x01030000
424
#define SOUTH_GROUP1_PMU_SUSCLK 0x01030001
425
#define SOUTH_GROUP1_ADR_TRIGGER 0x01030002
426
#define SOUTH_GROUP1_PMU_AC_PRESENT 0x01030002
427
#define SOUTH_GROUP1_PMU_SLP_S45_N 0x01030003
428
#define SOUTH_GROUP1_PMU_SLP_S3_N 0x01030004
429
#define SOUTH_GROUP1_PMU_WAKE_N 0x01030005
430
#define SOUTH_GROUP1_PMU_PWRBTN_N 0x01030006
431
#define SOUTH_GROUP1_PMU_RESETBUTTON_N 0x01030007
432
#define SOUTH_GROUP1_PMU_PLTRST_N 0x01030008
433
#define SOUTH_GROUP1_SUS_STAT_N 0x01030009
434
#define SOUTH_GROUP1_SLP_S0IX_N 0x0103000A
435
#define SOUTH_GROUP1_SPI_CS0_N 0x0103000B
436
#define SOUTH_GROUP1_SPI_CS1_N 0x0103000C
437
#define SOUTH_GROUP1_SPI_MOSI_IO0 0x0103000D
438
#define SOUTH_GROUP1_SPI_MISO_IO1 0x0103000E
439
#define SOUTH_GROUP1_SPI_IO2 0x0103000F
440
#define SOUTH_GROUP1_SPI_IO3 0x01030010
441
#define SOUTH_GROUP1_SPI_CLK 0x01030011
442
#define SOUTH_GROUP1_SPI_CLK_LOOPBK 0x01030012
443
#define SOUTH_GROUP1_ESPI_IO0 0x01030013
444
#define SOUTH_GROUP1_ESPI_IO1 0x01030014
445
#define SOUTH_GROUP1_ESPI_IO2 0x01030015
446
#define SOUTH_GROUP1_ESPI_IO3 0x01030016
447
#define SOUTH_GROUP1_ESPI_CS0_N 0x01030017
448
#define SOUTH_GROUP1_ESPI_CLK 0x01030018
449
#define SOUTH_GROUP1_ESPI_RST_N 0x01030019
450
#define SOUTH_GROUP1_ESPI_ALRT0_N 0x0103001A
451
#define SOUTH_GROUP1_GPIO_10 0x0103001B
452
#define SOUTH_GROUP1_GPIO_11 0x0103001C
453
#define SOUTH_GROUP1_ESPI_CLK_LOOPBK 0x0103001D
454
#define SOUTH_GROUP1_EMMC_CMD 0x0103001E
455
#define SOUTH_GROUP1_EMMC_STROBE 0x0103001F
456
#define SOUTH_GROUP1_EMMC_CLK 0x01030020
457
#define SOUTH_GROUP1_EMMC_D0 0x01030021
458
#define SOUTH_GROUP1_EMMC_D1 0x01030022
459
#define SOUTH_GROUP1_EMMC_D2 0x01030023
460
#define SOUTH_GROUP1_EMMC_D3 0x01030024
461
#define SOUTH_GROUP1_EMMC_D4 0x01030025
462
#define SOUTH_GROUP1_EMMC_D5 0x01030026
463
#define SOUTH_GROUP1_EMMC_D6 0x01030027
464
#define SOUTH_GROUP1_EMMC_D7 0x01030028
465
#define SOUTH_GROUP1_GPIO_3 0x01030029
466
467
// BIT15-0 - pad number
468
// BIT31-16 - group info
469
// BIT23- 16 - group index
470
// BIT31- 24 - chipset ID (default to 0x01)
471
#define PAD_INFO_MASK 0x0000FFFF
472
#define GROUP_INFO_POSITION 16
473
#define GROUP_INFO_MASK 0xFFFF0000
474
#define GROUP_INDEX_MASK 0x00FF0000
475
#define UNIQUE_ID_MASK 0xFF000000
476
#define UNIQUE_ID_POSITION 24
477
478
#define GPIO_PAD_DEF(Group, Pad) (uint32_t)((Group << 16) + Pad)
479
#define GPIO_GET_GROUP_INDEX(Group) (Group & 0xFF)
480
#define GPIO_GET_GROUP_FROM_PAD(Pad) (Pad >> 16)
481
#define GPIO_GET_GROUP_INDEX_FROM_PAD(Pad) GPIO_GET_GROUP_INDEX((Pad >> 16))
482
#define GPIO_GET_PAD_NUMBER(Pad) (Pad & 0xFFFF)
483
#define GPIO_GET_CHIPSET_ID(Pad) (Pad >> 24)
484
485
#endif
/* _DENVERTON_NS_GPIO_DEFS_H_ */
pcr.h
src
soc
intel
denverton_ns
include
soc
gpio_defs.h
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