coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
variant.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <acpi/acpi.h>
5 #include <baseboard/variants.h>
6 #include <variant/sku.h>
7 #include <gpio.h>
8 #include <variant/gpio.h>
9 
10 static const struct soc_amd_gpio variant_gpio_wlan_rst_early_reset[] = {
11  /* GPIO_70 - WLAN_PE_RST_L */
12  PAD_GPO(GPIO_70, LOW),
13 };
14 
16 {
19 }
20 
22 {
24  uint32_t bid;
25 
26  if (!acpi_is_wakeup_s3()) {
27  /* Based on SKU, turn on keyboard backlight */
28  switch (sku) {
29  default:
31  break;
37  break;
38  }
39  }
40 
42 
43  if (bid == 7)
44  /*
45  * Config WLAN RST - GPIO70 PU: release RST
46  * From RTK RTL8822CE spec, WLAN RST needs to be active
47  * at least 50 ms since WLAN power on
48  */
49  gpio_set(GPIO_70, 1);
50 }
static int acpi_is_wakeup_s3(void)
Definition: acpi.h:9
#define ARRAY_SIZE(a)
Definition: helpers.h:12
int google_chromeec_get_board_version(uint32_t *version)
google_chromeec_get_board_version() - Get the board version
Definition: ec.c:915
uint32_t google_chromeec_get_sku_id(void)
Definition: ec.c:934
int google_chromeec_kbbacklight(int percent)
Definition: ec.c:75
const struct soc_amd_gpio * variant_wlan_rst_early_gpio_table(size_t *size)
Definition: variant.c:15
void variant_romstage_entry(void)
Definition: variant.c:21
static const struct soc_amd_gpio variant_gpio_wlan_rst_early_reset[]
Definition: variant.c:10
enum project_sku sku
Definition: mainboard.c:51
void gpio_set(gpio_t gpio, int value)
Definition: gpio.c:174
@ SKU_CAREENA_KB_BACKLIGHT23
Definition: sku.h:10
@ SKU_CAREENA_KB_BACKLIGHT22
Definition: sku.h:9
@ SKU_CAREENA_KB_BACKLIGHT18
Definition: sku.h:7
@ SKU_CAREENA_KB_BACKLIGHT19
Definition: sku.h:8
#define GPIO_70
Definition: gpio.h:56
#define PAD_GPO(pin, direction)
Definition: gpio_defs.h:220
unsigned int uint32_t
Definition: stdint.h:14