coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Data Fields
southbridge_intel_lynxpoint_config Struct Reference

#include <chip.h>

Collaboration diagram for southbridge_intel_lynxpoint_config:
Collaboration graph

Data Fields

uint8_t gpi0_routing
 GPI Routing configuration for LynxPoint-H. More...
 
uint8_t gpi1_routing
 
uint8_t gpi2_routing
 
uint8_t gpi3_routing
 
uint8_t gpi4_routing
 
uint8_t gpi5_routing
 
uint8_t gpi6_routing
 
uint8_t gpi7_routing
 
uint8_t gpi8_routing
 
uint8_t gpi9_routing
 
uint8_t gpi10_routing
 
uint8_t gpi11_routing
 
uint8_t gpi12_routing
 
uint8_t gpi13_routing
 
uint8_t gpi14_routing
 
uint8_t gpi15_routing
 
uint32_t gpe0_en_1
 
uint32_t gpe0_en_2
 
uint32_t gpe0_en_3
 
uint32_t gpe0_en_4
 
uint32_t alt_gp_smi_en
 
uint8_t sata_port_map
 
uint32_t sata_port0_gen3_tx
 
uint32_t sata_port1_gen3_tx
 
uint32_t sata_port0_gen3_dtle
 
uint32_t sata_port1_gen3_dtle
 
uint8_t sata_devslp_mux
 
uint8_t sata_devslp_disable
 
uint32_t gen1_dec
 
uint32_t gen2_dec
 
uint32_t gen3_dec
 
uint32_t gen4_dec
 
bool pcie_port_coalesce
 
uint8_t pcie_port_force_aspm
 
uint8_t sio_acpi_mode
 
uint8_t sio_i2c0_voltage
 
uint8_t sio_i2c1_voltage
 
uint32_t icc_clock_disable
 
uint8_t xhci_default
 
bool docking_supported
 

Detailed Description

Definition at line 8 of file chip.h.

Field Documentation

◆ alt_gp_smi_en

uint32_t southbridge_intel_lynxpoint_config::alt_gp_smi_en

Definition at line 39 of file chip.h.

◆ docking_supported

bool southbridge_intel_lynxpoint_config::docking_supported

Definition at line 91 of file chip.h.

Referenced by acpi_fill_fadt().

◆ gen1_dec

uint32_t southbridge_intel_lynxpoint_config::gen1_dec

Definition at line 62 of file chip.h.

◆ gen2_dec

uint32_t southbridge_intel_lynxpoint_config::gen2_dec

Definition at line 63 of file chip.h.

◆ gen3_dec

uint32_t southbridge_intel_lynxpoint_config::gen3_dec

Definition at line 64 of file chip.h.

◆ gen4_dec

uint32_t southbridge_intel_lynxpoint_config::gen4_dec

Definition at line 65 of file chip.h.

◆ gpe0_en_1

uint32_t southbridge_intel_lynxpoint_config::gpe0_en_1

Definition at line 35 of file chip.h.

◆ gpe0_en_2

uint32_t southbridge_intel_lynxpoint_config::gpe0_en_2

Definition at line 36 of file chip.h.

◆ gpe0_en_3

uint32_t southbridge_intel_lynxpoint_config::gpe0_en_3

Definition at line 37 of file chip.h.

◆ gpe0_en_4

uint32_t southbridge_intel_lynxpoint_config::gpe0_en_4

Definition at line 38 of file chip.h.

◆ gpi0_routing

uint8_t southbridge_intel_lynxpoint_config::gpi0_routing

GPI Routing configuration for LynxPoint-H.

Only the lower two bits have a meaning: 00: No effect 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 10: SCI (if corresponding GPIO_EN bit is also set) 11: reserved

Definition at line 18 of file chip.h.

◆ gpi10_routing

uint8_t southbridge_intel_lynxpoint_config::gpi10_routing

Definition at line 28 of file chip.h.

◆ gpi11_routing

uint8_t southbridge_intel_lynxpoint_config::gpi11_routing

Definition at line 29 of file chip.h.

◆ gpi12_routing

uint8_t southbridge_intel_lynxpoint_config::gpi12_routing

Definition at line 30 of file chip.h.

◆ gpi13_routing

uint8_t southbridge_intel_lynxpoint_config::gpi13_routing

Definition at line 31 of file chip.h.

◆ gpi14_routing

uint8_t southbridge_intel_lynxpoint_config::gpi14_routing

Definition at line 32 of file chip.h.

◆ gpi15_routing

uint8_t southbridge_intel_lynxpoint_config::gpi15_routing

Definition at line 33 of file chip.h.

◆ gpi1_routing

uint8_t southbridge_intel_lynxpoint_config::gpi1_routing

Definition at line 19 of file chip.h.

◆ gpi2_routing

uint8_t southbridge_intel_lynxpoint_config::gpi2_routing

Definition at line 20 of file chip.h.

◆ gpi3_routing

uint8_t southbridge_intel_lynxpoint_config::gpi3_routing

Definition at line 21 of file chip.h.

◆ gpi4_routing

uint8_t southbridge_intel_lynxpoint_config::gpi4_routing

Definition at line 22 of file chip.h.

◆ gpi5_routing

uint8_t southbridge_intel_lynxpoint_config::gpi5_routing

Definition at line 23 of file chip.h.

◆ gpi6_routing

uint8_t southbridge_intel_lynxpoint_config::gpi6_routing

Definition at line 24 of file chip.h.

◆ gpi7_routing

uint8_t southbridge_intel_lynxpoint_config::gpi7_routing

Definition at line 25 of file chip.h.

◆ gpi8_routing

uint8_t southbridge_intel_lynxpoint_config::gpi8_routing

Definition at line 26 of file chip.h.

◆ gpi9_routing

uint8_t southbridge_intel_lynxpoint_config::gpi9_routing

Definition at line 27 of file chip.h.

◆ icc_clock_disable

uint32_t southbridge_intel_lynxpoint_config::icc_clock_disable

Definition at line 85 of file chip.h.

◆ pcie_port_coalesce

bool southbridge_intel_lynxpoint_config::pcie_port_coalesce

Definition at line 68 of file chip.h.

◆ pcie_port_force_aspm

uint8_t southbridge_intel_lynxpoint_config::pcie_port_force_aspm

Definition at line 71 of file chip.h.

◆ sata_devslp_disable

uint8_t southbridge_intel_lynxpoint_config::sata_devslp_disable

Definition at line 60 of file chip.h.

◆ sata_devslp_mux

uint8_t southbridge_intel_lynxpoint_config::sata_devslp_mux

Definition at line 53 of file chip.h.

◆ sata_port0_gen3_dtle

uint32_t southbridge_intel_lynxpoint_config::sata_port0_gen3_dtle

Definition at line 45 of file chip.h.

◆ sata_port0_gen3_tx

uint32_t southbridge_intel_lynxpoint_config::sata_port0_gen3_tx

Definition at line 43 of file chip.h.

◆ sata_port1_gen3_dtle

uint32_t southbridge_intel_lynxpoint_config::sata_port1_gen3_dtle

Definition at line 46 of file chip.h.

◆ sata_port1_gen3_tx

uint32_t southbridge_intel_lynxpoint_config::sata_port1_gen3_tx

Definition at line 44 of file chip.h.

◆ sata_port_map

uint8_t southbridge_intel_lynxpoint_config::sata_port_map

Definition at line 42 of file chip.h.

◆ sio_acpi_mode

uint8_t southbridge_intel_lynxpoint_config::sio_acpi_mode

Definition at line 74 of file chip.h.

◆ sio_i2c0_voltage

uint8_t southbridge_intel_lynxpoint_config::sio_i2c0_voltage

Definition at line 77 of file chip.h.

◆ sio_i2c1_voltage

uint8_t southbridge_intel_lynxpoint_config::sio_i2c1_voltage

Definition at line 78 of file chip.h.

◆ xhci_default

uint8_t southbridge_intel_lynxpoint_config::xhci_default

Definition at line 88 of file chip.h.

The documentation for this struct was generated from the following file: