coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
infracfg.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /*
4  * This file is created based on MT8186 Functional Specification
5  * Chapter number: 4.5
6  */
7 
8 #ifndef SOC_MEDIATEK_MT8186_INFRACFG_H
9 #define SOC_MEDIATEK_MT8186_INFRACFG_H
10 
11 #include <soc/addressmap.h>
12 #include <types.h>
13 
14 struct mt8186_infracfg_ao_regs {
15  u32 reserved1[20];
16  u32 infra_globalcon_dcmctl;
17  u32 reserved2[7];
18  u32 infra_bus_dcm_ctrl;
19  u32 peri_bus_dcm_ctrl;
20  u32 mem_dcm_ctrl;
21  u32 dfs_mem_dcm_ctrl;
22  u32 module_sw_cg_0_set;
23  u32 module_sw_cg_0_clr;
24  u32 module_sw_cg_1_set;
25  u32 module_sw_cg_1_clr;
26  u32 module_sw_cg_0_sta;
27  u32 module_sw_cg_1_sta;
28  u32 module_clk_sel;
29  u32 mem_cg_ctrl;
30  u32 p2p_rx_clk_on;
31  u32 module_sw_cg_2_set;
32  u32 module_sw_cg_2_clr;
33  u32 module_sw_cg_2_sta;
34  u32 reserved3[1];
35  u32 dramc_wbr;
36  u32 ddr_en_mask;
37  u32 reserved4[1];
38  u32 module_sw_cg_3_set;
39  u32 module_sw_cg_3_clr;
40  u32 module_sw_cg_3_sta;
41  u32 reserved5[13];
42  u32 i2c_dbtool_misc;
43  u32 md_sleep_ctrl_mask;
44  u32 pmicw_clock_ctrl;
45  u32 reserved6[5];
46  u32 infra_globalcon_rst0_set;
47  u32 infra_globalcon_rst0_clr;
48  u32 infra_globalcon_rst0_sta;
49  u32 reserved7[1];
50  u32 infra_globalcon_rst1_set;
51  u32 infra_globalcon_rst1_clr;
52  u32 infra_globalcon_rst1_sta;
53  u32 reserved8[1];
54  u32 infra_globalcon_rst2_set;
55  u32 infra_globalcon_rst2_clr;
56  u32 infra_globalcon_rst2_sta;
57  u32 reserved9[1];
58  u32 infra_globalcon_rst3_set;
59  u32 infra_globalcon_rst3_clr;
60  u32 infra_globalcon_rst3_sta;
61  u32 reserved10[41];
62  u32 infra_topaxi_si0_ctl;
63  u32 infra_topaxi_si1_ctl;
64  u32 infra_topaxi_mdbus_ctl;
65  u32 infra_mci_si0_ctl;
66  u32 infra_mci_si1_ctl;
67  u32 infra_mci_si2_ctl;
68  u32 infra_mci_async_ctl;
69  u32 infra_mci_cg_mfg_sec_sta;
70  u32 infra_topaxi_protecten;
71  u32 infra_topaxi_protecten_sta0;
72  u32 infra_topaxi_protecten_sta1;
73  u32 infra_axi_aslice_ctrl;
74  u32 infra_apb_async_sta;
75  u32 infra_topaxi_si2_ctl;
76  u32 reserved11[1];
77  u32 infra_topaxi_trans_limiter_1;
78  u32 infra_mci_trans_con_read;
79  u32 infra_mci_trans_con_write;
80  u32 infra_mci_id_remap_con;
81  u32 infra_mci_emi_trans_con;
82  u32 infra_topaxi_protecten_1;
83  u32 infra_topaxi_protecten_sta0_1;
84  u32 infra_topaxi_protecten_sta1_1;
85  u32 reserved12[1];
86  u32 infra_topaxi_aslice_ctrl;
87  u32 infra_topaxi_protecten_2;
88  u32 infra_topaxi_protecten_sta0_2;
89  u32 infra_topaxi_protecten_sta1_2;
90  u32 infra_topaxi_mi_ctrl;
91  u32 infra_topaxi_cbip_aslice_ctrl;
92  u32 infra_topaxi_cbip_slice_ctrl;
93  u32 infra_top_master_sideband;
94  u32 reserved13[1];
95  u32 infra_topaxi_trans_limiter;
96  u32 infra_topaxi_emi_gmc_l2c_ctrl;
97  u32 infra_topaxi_cbip_slice_ctrl_1;
98  u32 infra_mfg_slave_gals_ctrl;
99  u32 infra_mfg_master_m0_gals_ctrl;
100  u32 infra_mfg_master_m1_gals_ctrl;
101  u32 infra_top_master_sideband_1;
102  u32 infra_topaxi_protecten_set;
103  u32 infra_topaxi_protecten_clr;
104  u32 infra_topaxi_protecten_1_set;
105  u32 infra_topaxi_protecten_1_clr;
106  u32 infra_topaxi_protecten_2_set;
107  u32 infra_topaxi_protecten_2_clr;
108  u32 infra_topaxi_protecten_3_set;
109  u32 infra_topaxi_protecten_3_clr;
110  u32 infra_topaxi_protecten_3;
111  u32 infra_topaxi_protecten_sta0_3;
112  u32 infra_topaxi_protecten_sta1_3;
113  u32 reserved14[12];
114  u32 infra_topaxi_bus_dbg_con_a0;
115  u32 md1_bank0_map0;
116  u32 md1_bank0_map1;
117  u32 md1_bank0_map2;
118  u32 md1_bank0_map3;
119  u32 md1_bank1_map0;
120  u32 md1_bank1_map1;
121  u32 md1_bank1_map2;
122  u32 md1_bank1_map3;
123  u32 md1_bank4_map0;
124  u32 md1_bank4_map1;
125  u32 md1_bank4_map2;
126  u32 md1_bank4_map3;
127  u32 md2_bank0_map0;
128  u32 md2_bank0_map1;
129  u32 md2_bank0_map2;
130  u32 md2_bank0_map3;
131  u32 reserved15[4];
132  u32 md2_bank4_map0;
133  u32 md2_bank4_map1;
134  u32 md2_bank4_map2;
135  u32 md2_bank4_map3;
136  u32 c2k_config;
137  u32 c2k_status;
138  u32 c2k_spm_ctrl;
139  u32 reserved16[1];
140  u32 ap2md_dummy;
141  u32 reserved17[3];
142  u32 conn_map0;
143  u32 cldma_map0;
144  u32 conn_map1;
145  u32 conn_bus_con;
146  u32 mcusys_dfd_map;
147  u32 reserved18[1];
148  u32 conn_map3;
149  u32 conn_map4;
150  u32 reserved19[24];
151  u32 peri_cci_sideband_con;
152  u32 mfg_cci_sideband_con;
153  u32 reserved20[2];
154  u32 infra_pwm_cksw_ctrl;
155  u32 reserved21[59];
156  u32 infra_ao_dbg_con0;
157  u32 infra_ao_dbg_con1;
158  u32 infra_ao_dbg_con2;
159  u32 infra_ao_dbg_con3;
160  u32 md_dbg_ck_con;
161  u32 reserved22[59];
162  u32 mfg_misc_con;
163  u32 reserved23[62];
164  u32 infra_msdc_con;
165  u32 infra_rsvd0;
166  u32 infra_rsvd1;
167  u32 infra_rsvd2;
168  u32 infra_rsvd3;
169  u32 infra_rsvd4;
170  u32 infra_rsvd5;
171  u32 infra_iommu_en;
172  u32 reserved24[89];
173  u32 md1_sbc_key0;
174  u32 md1_sbc_key1;
175  u32 md1_sbc_key2;
176  u32 md1_sbc_key3;
177  u32 md1_sbc_key4;
178  u32 md1_sbc_key5;
179  u32 md1_sbc_key6;
180  u32 md1_sbc_key7;
181  u32 md1_sbc_key_lock;
182  u32 reserved25[1];
183  u32 md1_misc_lock;
184  u32 md1_misc;
185  u32 c2k_sbc_key0;
186  u32 c2k_sbc_key1;
187  u32 c2k_sbc_key2;
188  u32 c2k_sbc_key3;
189  u32 c2k_sbc_key4;
190  u32 c2k_sbc_key5;
191  u32 c2k_sbc_key6;
192  u32 c2k_sbc_key7;
193  u32 c2k_sbc_key_lock;
194  u32 reserved26[11];
195  u32 infra_bonding;
196  u32 subsys_pdn_nohang_dis0;
197  u32 subsys_pdn_nohang_dis1;
198  u32 reserved27[61];
199  u32 infra_ao_scpsys_apb_async_sta;
200  u32 infra_ao_md32_tx_apb_async_sta;
201  u32 infra_ao_md32_rx_apb_async_sta;
202  u32 infra_ao_cksys_apb_async_sta;
203  u32 infra_ao_pmic_wrap_tx_apb_async_sta;
204  u32 infra_ao_pmif_spmi_tx_apb_async_sta;
205  u32 infra_ao_spmi_mst_tx_apb_async_sta;
206  u32 infra_ao_infra0_iommu_apb_async_sta;
207  u32 infra_ao_infra1_iommu_apb_async_sta;
208  u32 reserved28[6];
209  u32 infra_ao_mcu_pwr_mask;
210  u32 reserved29[48];
211  u32 pll_ulposc_con0;
212  u32 pll_ulposc_con1;
213  u32 reserved30[2];
214  u32 pll_auxadc_con0;
215  u32 scp_infra_irq_set;
216  u32 scp_infra_irq_clr;
217  u32 scp_infra_ctrl;
218  u32 conn2infra_gals_dbg;
219  u32 infra_infra2adsp_axi_gals_debug;
220  u32 infra_adsp2infra_axi_gals_debug;
221  u32 infra_adsp2emi_axi_gals_debug;
222  u32 nna0_1_emi_axi_gals_debug;
223  u32 nna2_emi_axi_gals_debug;
224  u32 nn2infra_axi_gals_debug;
225  u32 infra2nna_axi_gals_debug;
226  u32 reserved31[48];
227  u32 cldma_ctrl;
228  u32 reserved32[3];
229  u32 rg_ccif4_md_pwr_flag;
230  u32 rg_ccif4_con_pwr_flag;
231  u32 rd_ccif4_cpu_pwr_flag;
232  u32 reserved33[1];
233  u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_set_ctrl_0;
234  u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_clr_ctrl_0;
235  u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_rw_ctrl_0;
236  u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_ro_ctrl_0;
237  u32 infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi_pwr_prot_ctrl_0;
238  u32 infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi2sbus_ctrl_0;
239  u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip0sys_bus_asl7_axi_pwr_prot_ctrl_0;
240  u32 reserved34[1];
241  u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip1sys_bus_asl8_axi_pwr_prot_ctrl_0;
242  u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip2sys_bus_asl9_axi_pwr_prot_ctrl_0;
243  u32 infra_ipsys_s_bus_u_si0_ctrl_0;
244  u32 infra_ipsys_s_bus_u_si0_ctrl_1;
245  u32 infra_ipsys_s_bus_u_si0_ctrl_2;
246  u32 infra_ipsys_s_bus_u_si0_ctrl_3;
247  u32 infra_ipsys_s_bus_u_si0_ctrl_4;
248  u32 infra_ipsys_s_bus_u_si0_ctrl_5;
249  u32 reserved35[40];
250  u32 infrabus_dbg0;
251  u32 infrabus_dbg1;
252  u32 infrabus_dbg2;
253  u32 infrabus_dbg3;
254  u32 infrabus_dbg4;
255  u32 infrabus_dbg5;
256  u32 infrabus_dbg6;
257  u32 infrabus_dbg7;
258  u32 infrabus_dbg8;
259  u32 infrabus_dbg9;
260  u32 infrabus_dbg10;
261  u32 infrabus_dbg11;
262  u32 infrabus_dbg12;
263  u32 infrabus_dbg13;
264  u32 infrabus_dbg14;
265  u32 infrabus_dbg15;
266  u32 infrabus_dbg16;
267  u32 reserved36[111];
268  u32 infra_misc;
269  u32 infra_acp;
270  u32 misc_config;
271  u32 infra_misc2;
272  u32 mdsys_misc_con;
273  u32 reserved37[12];
274  u32 nna_infra_gals_ctrl;
275  u32 nna_emi_gals_ctrl;
276  u32 infra_adsp_infra_gals_ctrl;
277  u32 infra_adsp_emi_gals_ctrl;
278  u32 reserved38[11];
279  u32 infra_ao_sec_con;
280  u32 infra_ao_sec_cg_con0;
281  u32 infra_ao_sec_cg_con1;
282  u32 infra_ao_sec_rst_con0;
283  u32 infra_ao_sec_rst_con1;
284  u32 infra_ao_sec_rst_con2;
285  u32 dxcc_dcu_en_lock;
286  u32 infra_ao_sec_cg_con2;
287  u32 infra_ao_sec_rst_con3;
288  u32 infra_ao_sec_cg_con3;
289  u32 reserved39[2];
290  u32 infra_ao_sec_hyp;
291  u32 infra_mcu2emi_slice;
292  u32 infra_ao_sec_mfg_hyp;
293 };
294 
295 check_member(mt8186_infracfg_ao_regs, infra_globalcon_dcmctl, 0x50);
296 check_member(mt8186_infracfg_ao_regs, infra_bus_dcm_ctrl, 0x70);
297 check_member(mt8186_infracfg_ao_regs, peri_bus_dcm_ctrl, 0x74);
298 check_member(mt8186_infracfg_ao_regs, mem_dcm_ctrl, 0x78);
299 check_member(mt8186_infracfg_ao_regs, dfs_mem_dcm_ctrl, 0x7c);
300 check_member(mt8186_infracfg_ao_regs, module_sw_cg_0_set, 0x80);
301 check_member(mt8186_infracfg_ao_regs, module_sw_cg_0_clr, 0x84);
302 check_member(mt8186_infracfg_ao_regs, module_sw_cg_1_set, 0x88);
303 check_member(mt8186_infracfg_ao_regs, module_sw_cg_1_clr, 0x8c);
304 check_member(mt8186_infracfg_ao_regs, module_sw_cg_0_sta, 0x90);
305 check_member(mt8186_infracfg_ao_regs, module_sw_cg_1_sta, 0x94);
306 check_member(mt8186_infracfg_ao_regs, module_clk_sel, 0x98);
307 check_member(mt8186_infracfg_ao_regs, mem_cg_ctrl, 0x9c);
308 check_member(mt8186_infracfg_ao_regs, p2p_rx_clk_on, 0xa0);
309 check_member(mt8186_infracfg_ao_regs, module_sw_cg_2_set, 0xa4);
310 check_member(mt8186_infracfg_ao_regs, module_sw_cg_2_clr, 0xa8);
311 check_member(mt8186_infracfg_ao_regs, module_sw_cg_2_sta, 0xac);
312 check_member(mt8186_infracfg_ao_regs, dramc_wbr, 0xb4);
313 check_member(mt8186_infracfg_ao_regs, ddr_en_mask, 0xb8);
314 check_member(mt8186_infracfg_ao_regs, module_sw_cg_3_set, 0xc0);
315 check_member(mt8186_infracfg_ao_regs, module_sw_cg_3_clr, 0xc4);
316 check_member(mt8186_infracfg_ao_regs, module_sw_cg_3_sta, 0xc8);
317 check_member(mt8186_infracfg_ao_regs, i2c_dbtool_misc, 0x100);
318 check_member(mt8186_infracfg_ao_regs, md_sleep_ctrl_mask, 0x104);
319 check_member(mt8186_infracfg_ao_regs, pmicw_clock_ctrl, 0x108);
320 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst0_set, 0x120);
321 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst0_clr, 0x124);
322 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst0_sta, 0x128);
323 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst1_set, 0x130);
324 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst1_clr, 0x134);
325 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst1_sta, 0x138);
326 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst2_set, 0x140);
327 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst2_clr, 0x144);
328 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst2_sta, 0x148);
329 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst3_set, 0x150);
330 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst3_clr, 0x154);
331 check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst3_sta, 0x158);
332 check_member(mt8186_infracfg_ao_regs, infra_topaxi_si0_ctl, 0x200);
333 check_member(mt8186_infracfg_ao_regs, infra_topaxi_si1_ctl, 0x204);
334 check_member(mt8186_infracfg_ao_regs, infra_topaxi_mdbus_ctl, 0x208);
335 check_member(mt8186_infracfg_ao_regs, infra_mci_si0_ctl, 0x20c);
336 check_member(mt8186_infracfg_ao_regs, infra_mci_si1_ctl, 0x210);
337 check_member(mt8186_infracfg_ao_regs, infra_mci_si2_ctl, 0x214);
338 check_member(mt8186_infracfg_ao_regs, infra_mci_async_ctl, 0x218);
339 check_member(mt8186_infracfg_ao_regs, infra_mci_cg_mfg_sec_sta, 0x21c);
340 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten, 0x220);
341 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0, 0x224);
342 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1, 0x228);
343 check_member(mt8186_infracfg_ao_regs, infra_axi_aslice_ctrl, 0x22c);
344 check_member(mt8186_infracfg_ao_regs, infra_apb_async_sta, 0x230);
345 check_member(mt8186_infracfg_ao_regs, infra_topaxi_si2_ctl, 0x234);
346 check_member(mt8186_infracfg_ao_regs, infra_topaxi_trans_limiter_1, 0x23c);
347 check_member(mt8186_infracfg_ao_regs, infra_mci_trans_con_read, 0x240);
348 check_member(mt8186_infracfg_ao_regs, infra_mci_trans_con_write, 0x244);
349 check_member(mt8186_infracfg_ao_regs, infra_mci_id_remap_con, 0x248);
350 check_member(mt8186_infracfg_ao_regs, infra_mci_emi_trans_con, 0x24c);
351 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_1, 0x250);
352 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0_1, 0x254);
353 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1_1, 0x258);
354 check_member(mt8186_infracfg_ao_regs, infra_topaxi_aslice_ctrl, 0x260);
355 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_2, 0x264);
356 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0_2, 0x268);
357 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1_2, 0x26c);
358 check_member(mt8186_infracfg_ao_regs, infra_topaxi_mi_ctrl, 0x270);
359 check_member(mt8186_infracfg_ao_regs, infra_topaxi_cbip_aslice_ctrl, 0x274);
360 check_member(mt8186_infracfg_ao_regs, infra_topaxi_cbip_slice_ctrl, 0x278);
361 check_member(mt8186_infracfg_ao_regs, infra_top_master_sideband, 0x27c);
362 check_member(mt8186_infracfg_ao_regs, infra_topaxi_trans_limiter, 0x284);
363 check_member(mt8186_infracfg_ao_regs, infra_topaxi_emi_gmc_l2c_ctrl, 0x288);
364 check_member(mt8186_infracfg_ao_regs, infra_topaxi_cbip_slice_ctrl_1, 0x28c);
365 check_member(mt8186_infracfg_ao_regs, infra_mfg_slave_gals_ctrl, 0x290);
366 check_member(mt8186_infracfg_ao_regs, infra_mfg_master_m0_gals_ctrl, 0x294);
367 check_member(mt8186_infracfg_ao_regs, infra_mfg_master_m1_gals_ctrl, 0x298);
368 check_member(mt8186_infracfg_ao_regs, infra_top_master_sideband_1, 0x29c);
369 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_set, 0x2a0);
370 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_clr, 0x2a4);
371 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_1_set, 0x2a8);
372 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_1_clr, 0x2ac);
373 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_2_set, 0x2b0);
374 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_2_clr, 0x2b4);
375 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_3_set, 0x2b8);
376 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_3_clr, 0x2bc);
377 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_3, 0x2c0);
378 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0_3, 0x2c4);
379 check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1_3, 0x2c8);
380 check_member(mt8186_infracfg_ao_regs, infra_topaxi_bus_dbg_con_a0, 0x2fc);
381 check_member(mt8186_infracfg_ao_regs, md1_bank0_map0, 0x300);
382 check_member(mt8186_infracfg_ao_regs, md1_bank0_map1, 0x304);
383 check_member(mt8186_infracfg_ao_regs, md1_bank0_map2, 0x308);
384 check_member(mt8186_infracfg_ao_regs, md1_bank0_map3, 0x30c);
385 check_member(mt8186_infracfg_ao_regs, md1_bank1_map0, 0x310);
386 check_member(mt8186_infracfg_ao_regs, md1_bank1_map1, 0x314);
387 check_member(mt8186_infracfg_ao_regs, md1_bank1_map2, 0x318);
388 check_member(mt8186_infracfg_ao_regs, md1_bank1_map3, 0x31c);
389 check_member(mt8186_infracfg_ao_regs, md1_bank4_map0, 0x320);
390 check_member(mt8186_infracfg_ao_regs, md1_bank4_map1, 0x324);
391 check_member(mt8186_infracfg_ao_regs, md1_bank4_map2, 0x328);
392 check_member(mt8186_infracfg_ao_regs, md1_bank4_map3, 0x32c);
393 check_member(mt8186_infracfg_ao_regs, md2_bank0_map0, 0x330);
394 check_member(mt8186_infracfg_ao_regs, md2_bank0_map1, 0x334);
395 check_member(mt8186_infracfg_ao_regs, md2_bank0_map2, 0x338);
396 check_member(mt8186_infracfg_ao_regs, md2_bank0_map3, 0x33c);
397 check_member(mt8186_infracfg_ao_regs, md2_bank4_map0, 0x350);
398 check_member(mt8186_infracfg_ao_regs, md2_bank4_map1, 0x354);
399 check_member(mt8186_infracfg_ao_regs, md2_bank4_map2, 0x358);
400 check_member(mt8186_infracfg_ao_regs, md2_bank4_map3, 0x35c);
401 check_member(mt8186_infracfg_ao_regs, c2k_config, 0x360);
402 check_member(mt8186_infracfg_ao_regs, c2k_status, 0x364);
403 check_member(mt8186_infracfg_ao_regs, c2k_spm_ctrl, 0x368);
404 check_member(mt8186_infracfg_ao_regs, ap2md_dummy, 0x370);
405 check_member(mt8186_infracfg_ao_regs, conn_map0, 0x380);
406 check_member(mt8186_infracfg_ao_regs, cldma_map0, 0x384);
407 check_member(mt8186_infracfg_ao_regs, conn_map1, 0x388);
408 check_member(mt8186_infracfg_ao_regs, conn_bus_con, 0x38c);
409 check_member(mt8186_infracfg_ao_regs, mcusys_dfd_map, 0x390);
410 check_member(mt8186_infracfg_ao_regs, conn_map3, 0x398);
411 check_member(mt8186_infracfg_ao_regs, conn_map4, 0x39c);
412 check_member(mt8186_infracfg_ao_regs, peri_cci_sideband_con, 0x400);
413 check_member(mt8186_infracfg_ao_regs, mfg_cci_sideband_con, 0x404);
414 check_member(mt8186_infracfg_ao_regs, infra_pwm_cksw_ctrl, 0x410);
415 check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con0, 0x500);
416 check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con1, 0x504);
417 check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con2, 0x508);
418 check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con3, 0x50c);
419 check_member(mt8186_infracfg_ao_regs, md_dbg_ck_con, 0x510);
420 check_member(mt8186_infracfg_ao_regs, mfg_misc_con, 0x600);
421 check_member(mt8186_infracfg_ao_regs, infra_msdc_con, 0x6fc);
422 check_member(mt8186_infracfg_ao_regs, infra_rsvd0, 0x700);
423 check_member(mt8186_infracfg_ao_regs, infra_rsvd1, 0x704);
424 check_member(mt8186_infracfg_ao_regs, infra_rsvd2, 0x708);
425 check_member(mt8186_infracfg_ao_regs, infra_rsvd3, 0x70c);
426 check_member(mt8186_infracfg_ao_regs, infra_rsvd4, 0x710);
427 check_member(mt8186_infracfg_ao_regs, infra_rsvd5, 0x714);
428 check_member(mt8186_infracfg_ao_regs, infra_iommu_en, 0x718);
429 check_member(mt8186_infracfg_ao_regs, md1_sbc_key0, 0x880);
430 check_member(mt8186_infracfg_ao_regs, md1_sbc_key1, 0x884);
431 check_member(mt8186_infracfg_ao_regs, md1_sbc_key2, 0x888);
432 check_member(mt8186_infracfg_ao_regs, md1_sbc_key3, 0x88c);
433 check_member(mt8186_infracfg_ao_regs, md1_sbc_key4, 0x890);
434 check_member(mt8186_infracfg_ao_regs, md1_sbc_key5, 0x894);
435 check_member(mt8186_infracfg_ao_regs, md1_sbc_key6, 0x898);
436 check_member(mt8186_infracfg_ao_regs, md1_sbc_key7, 0x89c);
437 check_member(mt8186_infracfg_ao_regs, md1_sbc_key_lock, 0x8a0);
438 check_member(mt8186_infracfg_ao_regs, md1_misc_lock, 0x8a8);
439 check_member(mt8186_infracfg_ao_regs, md1_misc, 0x8ac);
440 check_member(mt8186_infracfg_ao_regs, c2k_sbc_key0, 0x8b0);
441 check_member(mt8186_infracfg_ao_regs, c2k_sbc_key1, 0x8b4);
442 check_member(mt8186_infracfg_ao_regs, c2k_sbc_key2, 0x8b8);
443 check_member(mt8186_infracfg_ao_regs, c2k_sbc_key3, 0x8bc);
444 check_member(mt8186_infracfg_ao_regs, c2k_sbc_key4, 0x8c0);
445 check_member(mt8186_infracfg_ao_regs, c2k_sbc_key5, 0x8c4);
446 check_member(mt8186_infracfg_ao_regs, c2k_sbc_key6, 0x8c8);
447 check_member(mt8186_infracfg_ao_regs, c2k_sbc_key7, 0x8cc);
448 check_member(mt8186_infracfg_ao_regs, c2k_sbc_key_lock, 0x8d0);
449 check_member(mt8186_infracfg_ao_regs, infra_bonding, 0x900);
450 check_member(mt8186_infracfg_ao_regs, subsys_pdn_nohang_dis0, 0x904);
451 check_member(mt8186_infracfg_ao_regs, subsys_pdn_nohang_dis1, 0x908);
452 check_member(mt8186_infracfg_ao_regs, infra_ao_scpsys_apb_async_sta, 0xa00);
453 check_member(mt8186_infracfg_ao_regs, infra_ao_md32_tx_apb_async_sta, 0xa04);
454 check_member(mt8186_infracfg_ao_regs, infra_ao_md32_rx_apb_async_sta, 0xa08);
455 check_member(mt8186_infracfg_ao_regs, infra_ao_cksys_apb_async_sta, 0xa0c);
456 check_member(mt8186_infracfg_ao_regs, infra_ao_pmic_wrap_tx_apb_async_sta, 0xa10);
457 check_member(mt8186_infracfg_ao_regs, infra_ao_pmif_spmi_tx_apb_async_sta, 0xa14);
458 check_member(mt8186_infracfg_ao_regs, infra_ao_spmi_mst_tx_apb_async_sta, 0xa18);
459 check_member(mt8186_infracfg_ao_regs, infra_ao_infra0_iommu_apb_async_sta, 0xa1c);
460 check_member(mt8186_infracfg_ao_regs, infra_ao_infra1_iommu_apb_async_sta, 0xa20);
461 check_member(mt8186_infracfg_ao_regs, infra_ao_mcu_pwr_mask, 0xa3c);
462 check_member(mt8186_infracfg_ao_regs, pll_ulposc_con0, 0xb00);
463 check_member(mt8186_infracfg_ao_regs, pll_ulposc_con1, 0xb04);
464 check_member(mt8186_infracfg_ao_regs, pll_auxadc_con0, 0xb10);
465 check_member(mt8186_infracfg_ao_regs, scp_infra_irq_set, 0xb14);
466 check_member(mt8186_infracfg_ao_regs, scp_infra_irq_clr, 0xb18);
467 check_member(mt8186_infracfg_ao_regs, scp_infra_ctrl, 0xb1c);
468 check_member(mt8186_infracfg_ao_regs, conn2infra_gals_dbg, 0xb20);
469 check_member(mt8186_infracfg_ao_regs, infra_infra2adsp_axi_gals_debug, 0xb24);
470 check_member(mt8186_infracfg_ao_regs, infra_adsp2infra_axi_gals_debug, 0xb28);
471 check_member(mt8186_infracfg_ao_regs, infra_adsp2emi_axi_gals_debug, 0xb2c);
472 check_member(mt8186_infracfg_ao_regs, nna0_1_emi_axi_gals_debug, 0xb30);
473 check_member(mt8186_infracfg_ao_regs, nna2_emi_axi_gals_debug, 0xb34);
474 check_member(mt8186_infracfg_ao_regs, nn2infra_axi_gals_debug, 0xb38);
475 check_member(mt8186_infracfg_ao_regs, infra2nna_axi_gals_debug, 0xb3c);
476 check_member(mt8186_infracfg_ao_regs, cldma_ctrl, 0xc00);
477 check_member(mt8186_infracfg_ao_regs, rg_ccif4_md_pwr_flag, 0xc10);
478 check_member(mt8186_infracfg_ao_regs, rg_ccif4_con_pwr_flag, 0xc14);
479 check_member(mt8186_infracfg_ao_regs, rd_ccif4_cpu_pwr_flag, 0xc18);
480 check_member(mt8186_infracfg_ao_regs,
481  infra_ipsys_s_bus_bcrm_extended_bus_protect_set_ctrl_0, 0xc20);
482 check_member(mt8186_infracfg_ao_regs,
483  infra_ipsys_s_bus_bcrm_extended_bus_protect_clr_ctrl_0, 0xc24);
484 check_member(mt8186_infracfg_ao_regs,
485  infra_ipsys_s_bus_bcrm_extended_bus_protect_rw_ctrl_0, 0xc28);
486 check_member(mt8186_infracfg_ao_regs,
487  infra_ipsys_s_bus_bcrm_extended_bus_protect_ro_ctrl_0, 0xc2c);
488 check_member(mt8186_infracfg_ao_regs,
489  infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi_pwr_prot_ctrl_0, 0xc30);
490 check_member(mt8186_infracfg_ao_regs,
491  infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi2sbus_ctrl_0, 0xc34);
492 check_member(mt8186_infracfg_ao_regs,
493  infra_ipsys_s_bus_u_lnk_si0_to_infra_ip0sys_bus_asl7_axi_pwr_prot_ctrl_0, 0xc38);
494 check_member(mt8186_infracfg_ao_regs,
495  infra_ipsys_s_bus_u_lnk_si0_to_infra_ip1sys_bus_asl8_axi_pwr_prot_ctrl_0, 0xc40);
496 check_member(mt8186_infracfg_ao_regs,
497  infra_ipsys_s_bus_u_lnk_si0_to_infra_ip2sys_bus_asl9_axi_pwr_prot_ctrl_0, 0xc44);
498 check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_0, 0xc48);
499 check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_1, 0xc4c);
500 check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_2, 0xc50);
501 check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_3, 0xc54);
502 check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_4, 0xc58);
503 check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_5, 0xc5c);
504 check_member(mt8186_infracfg_ao_regs, infrabus_dbg0, 0xd00);
505 check_member(mt8186_infracfg_ao_regs, infrabus_dbg1, 0xd04);
506 check_member(mt8186_infracfg_ao_regs, infrabus_dbg2, 0xd08);
507 check_member(mt8186_infracfg_ao_regs, infrabus_dbg3, 0xd0c);
508 check_member(mt8186_infracfg_ao_regs, infrabus_dbg4, 0xd10);
509 check_member(mt8186_infracfg_ao_regs, infrabus_dbg5, 0xd14);
510 check_member(mt8186_infracfg_ao_regs, infrabus_dbg6, 0xd18);
511 check_member(mt8186_infracfg_ao_regs, infrabus_dbg7, 0xd1c);
512 check_member(mt8186_infracfg_ao_regs, infrabus_dbg8, 0xd20);
513 check_member(mt8186_infracfg_ao_regs, infrabus_dbg9, 0xd24);
514 check_member(mt8186_infracfg_ao_regs, infrabus_dbg10, 0xd28);
515 check_member(mt8186_infracfg_ao_regs, infrabus_dbg11, 0xd2c);
516 check_member(mt8186_infracfg_ao_regs, infrabus_dbg12, 0xd30);
517 check_member(mt8186_infracfg_ao_regs, infrabus_dbg13, 0xd34);
518 check_member(mt8186_infracfg_ao_regs, infrabus_dbg14, 0xd38);
519 check_member(mt8186_infracfg_ao_regs, infrabus_dbg15, 0xd3c);
520 check_member(mt8186_infracfg_ao_regs, infrabus_dbg16, 0xd40);
521 check_member(mt8186_infracfg_ao_regs, infra_misc, 0xf00);
522 check_member(mt8186_infracfg_ao_regs, infra_acp, 0xf04);
523 check_member(mt8186_infracfg_ao_regs, misc_config, 0xf08);
524 check_member(mt8186_infracfg_ao_regs, infra_misc2, 0xf0c);
525 check_member(mt8186_infracfg_ao_regs, mdsys_misc_con, 0xf10);
526 check_member(mt8186_infracfg_ao_regs, nna_infra_gals_ctrl, 0xf44);
527 check_member(mt8186_infracfg_ao_regs, nna_emi_gals_ctrl, 0xf48);
528 check_member(mt8186_infracfg_ao_regs, infra_adsp_infra_gals_ctrl, 0xf4c);
529 check_member(mt8186_infracfg_ao_regs, infra_adsp_emi_gals_ctrl, 0xf50);
530 check_member(mt8186_infracfg_ao_regs, infra_ao_sec_con, 0xf80);
531 check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con0, 0xf84);
532 check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con1, 0xf88);
533 check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con0, 0xf8c);
534 check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con1, 0xf90);
535 check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con2, 0xf94);
536 check_member(mt8186_infracfg_ao_regs, dxcc_dcu_en_lock, 0xf98);
537 check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con2, 0xf9c);
538 check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con3, 0xfa0);
539 check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con3, 0xfa4);
540 check_member(mt8186_infracfg_ao_regs, infra_ao_sec_hyp, 0xfb0);
541 check_member(mt8186_infracfg_ao_regs, infra_mcu2emi_slice, 0xfb4);
542 check_member(mt8186_infracfg_ao_regs, infra_ao_sec_mfg_hyp, 0xfb8);
543 
544 static struct mt8186_infracfg_ao_regs *const mt8186_infracfg_ao =
545  (void *)INFRACFG_AO_BASE;
546 
547 #endif /* SOC_MEDIATEK_MT8186_INFRACFG_H */
check_member
check_member(mt8173_infracfg_regs, infra_pdn0, 0x40)
mt8186_infracfg_ao
static struct mt8186_infracfg_ao_regs *const mt8186_infracfg_ao
Definition: infracfg.h:544
INFRACFG_AO_BASE
@ INFRACFG_AO_BASE
Definition: addressmap.h:15
u32
uint32_t u32
Definition: stdint.h:51
mt8186_infracfg_ao_regs
Definition: infracfg.h:14
mt8186_infracfg_ao_regs::scp_infra_ctrl
u32 scp_infra_ctrl
Definition: infracfg.h:217
mt8186_infracfg_ao_regs::reserved30
u32 reserved30[2]
Definition: infracfg.h:213
mt8186_infracfg_ao_regs::infra_topaxi_si2_ctl
u32 infra_topaxi_si2_ctl
Definition: infracfg.h:75
mt8186_infracfg_ao_regs::md1_bank1_map2
u32 md1_bank1_map2
Definition: infracfg.h:121
mt8186_infracfg_ao_regs::infra_iommu_en
u32 infra_iommu_en
Definition: infracfg.h:171
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_u_si0_ctrl_5
u32 infra_ipsys_s_bus_u_si0_ctrl_5
Definition: infracfg.h:248
mt8186_infracfg_ao_regs::infra_misc2
u32 infra_misc2
Definition: infracfg.h:271
mt8186_infracfg_ao_regs::infrabus_dbg5
u32 infrabus_dbg5
Definition: infracfg.h:255
mt8186_infracfg_ao_regs::infra_topaxi_protecten_sta1_3
u32 infra_topaxi_protecten_sta1_3
Definition: infracfg.h:112
mt8186_infracfg_ao_regs::c2k_sbc_key5
u32 c2k_sbc_key5
Definition: infracfg.h:190
mt8186_infracfg_ao_regs::infra_topaxi_protecten_sta1_1
u32 infra_topaxi_protecten_sta1_1
Definition: infracfg.h:84
mt8186_infracfg_ao_regs::infra_topaxi_cbip_slice_ctrl_1
u32 infra_topaxi_cbip_slice_ctrl_1
Definition: infracfg.h:97
mt8186_infracfg_ao_regs::infra_ao_infra0_iommu_apb_async_sta
u32 infra_ao_infra0_iommu_apb_async_sta
Definition: infracfg.h:206
mt8186_infracfg_ao_regs::infrabus_dbg12
u32 infrabus_dbg12
Definition: infracfg.h:262
mt8186_infracfg_ao_regs::reserved4
u32 reserved4[1]
Definition: infracfg.h:37
mt8186_infracfg_ao_regs::reserved5
u32 reserved5[13]
Definition: infracfg.h:41
mt8186_infracfg_ao_regs::peri_bus_dcm_ctrl
u32 peri_bus_dcm_ctrl
Definition: infracfg.h:19
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_bcrm_extended_bus_protect_set_ctrl_0
u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_set_ctrl_0
Definition: infracfg.h:233
mt8186_infracfg_ao_regs::nna0_1_emi_axi_gals_debug
u32 nna0_1_emi_axi_gals_debug
Definition: infracfg.h:222
mt8186_infracfg_ao_regs::reserved27
u32 reserved27[61]
Definition: infracfg.h:198
mt8186_infracfg_ao_regs::module_sw_cg_3_clr
u32 module_sw_cg_3_clr
Definition: infracfg.h:39
mt8186_infracfg_ao_regs::reserved23
u32 reserved23[62]
Definition: infracfg.h:163
mt8186_infracfg_ao_regs::reserved37
u32 reserved37[12]
Definition: infracfg.h:273
mt8186_infracfg_ao_regs::module_sw_cg_0_set
u32 module_sw_cg_0_set
Definition: infracfg.h:22
mt8186_infracfg_ao_regs::infra_adsp_infra_gals_ctrl
u32 infra_adsp_infra_gals_ctrl
Definition: infracfg.h:276
mt8186_infracfg_ao_regs::md1_bank4_map2
u32 md1_bank4_map2
Definition: infracfg.h:125
mt8186_infracfg_ao_regs::infra_ao_spmi_mst_tx_apb_async_sta
u32 infra_ao_spmi_mst_tx_apb_async_sta
Definition: infracfg.h:205
mt8186_infracfg_ao_regs::md1_bank4_map3
u32 md1_bank4_map3
Definition: infracfg.h:126
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_bcrm_extended_bus_protect_clr_ctrl_0
u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_clr_ctrl_0
Definition: infracfg.h:234
mt8186_infracfg_ao_regs::mcusys_dfd_map
u32 mcusys_dfd_map
Definition: infracfg.h:146
mt8186_infracfg_ao_regs::md2_bank0_map3
u32 md2_bank0_map3
Definition: infracfg.h:130
mt8186_infracfg_ao_regs::c2k_sbc_key6
u32 c2k_sbc_key6
Definition: infracfg.h:191
mt8186_infracfg_ao_regs::infra_ao_sec_rst_con3
u32 infra_ao_sec_rst_con3
Definition: infracfg.h:287
mt8186_infracfg_ao_regs::infra_topaxi_mdbus_ctl
u32 infra_topaxi_mdbus_ctl
Definition: infracfg.h:64
mt8186_infracfg_ao_regs::mdsys_misc_con
u32 mdsys_misc_con
Definition: infracfg.h:272
mt8186_infracfg_ao_regs::infrabus_dbg15
u32 infrabus_dbg15
Definition: infracfg.h:265
mt8186_infracfg_ao_regs::infrabus_dbg8
u32 infrabus_dbg8
Definition: infracfg.h:258
mt8186_infracfg_ao_regs::c2k_config
u32 c2k_config
Definition: infracfg.h:136
mt8186_infracfg_ao_regs::infra_pwm_cksw_ctrl
u32 infra_pwm_cksw_ctrl
Definition: infracfg.h:154
mt8186_infracfg_ao_regs::module_sw_cg_2_sta
u32 module_sw_cg_2_sta
Definition: infracfg.h:33
mt8186_infracfg_ao_regs::infra_globalcon_rst2_set
u32 infra_globalcon_rst2_set
Definition: infracfg.h:54
mt8186_infracfg_ao_regs::infra_adsp_emi_gals_ctrl
u32 infra_adsp_emi_gals_ctrl
Definition: infracfg.h:277
mt8186_infracfg_ao_regs::infra_ao_sec_cg_con0
u32 infra_ao_sec_cg_con0
Definition: infracfg.h:280
mt8186_infracfg_ao_regs::infra_misc
u32 infra_misc
Definition: infracfg.h:268
mt8186_infracfg_ao_regs::reserved16
u32 reserved16[1]
Definition: infracfg.h:139
mt8186_infracfg_ao_regs::md1_bank1_map3
u32 md1_bank1_map3
Definition: infracfg.h:122
mt8186_infracfg_ao_regs::infrabus_dbg3
u32 infrabus_dbg3
Definition: infracfg.h:253
mt8186_infracfg_ao_regs::md_dbg_ck_con
u32 md_dbg_ck_con
Definition: infracfg.h:160
mt8186_infracfg_ao_regs::infra_globalcon_rst3_set
u32 infra_globalcon_rst3_set
Definition: infracfg.h:58
mt8186_infracfg_ao_regs::cldma_ctrl
u32 cldma_ctrl
Definition: infracfg.h:227
mt8186_infracfg_ao_regs::rg_ccif4_md_pwr_flag
u32 rg_ccif4_md_pwr_flag
Definition: infracfg.h:229
mt8186_infracfg_ao_regs::infra_topaxi_protecten_1_clr
u32 infra_topaxi_protecten_1_clr
Definition: infracfg.h:105
mt8186_infracfg_ao_regs::reserved35
u32 reserved35[40]
Definition: infracfg.h:249
mt8186_infracfg_ao_regs::reserved21
u32 reserved21[59]
Definition: infracfg.h:155
mt8186_infracfg_ao_regs::reserved7
u32 reserved7[1]
Definition: infracfg.h:49
mt8186_infracfg_ao_regs::infra_rsvd0
u32 infra_rsvd0
Definition: infracfg.h:165
mt8186_infracfg_ao_regs::infra_topaxi_trans_limiter_1
u32 infra_topaxi_trans_limiter_1
Definition: infracfg.h:77
mt8186_infracfg_ao_regs::scp_infra_irq_clr
u32 scp_infra_irq_clr
Definition: infracfg.h:216
mt8186_infracfg_ao_regs::infra_topaxi_protecten_sta1_2
u32 infra_topaxi_protecten_sta1_2
Definition: infracfg.h:89
mt8186_infracfg_ao_regs::reserved18
u32 reserved18[1]
Definition: infracfg.h:147
mt8186_infracfg_ao_regs::infra_topaxi_protecten_sta0_3
u32 infra_topaxi_protecten_sta0_3
Definition: infracfg.h:111
mt8186_infracfg_ao_regs::infrabus_dbg11
u32 infrabus_dbg11
Definition: infracfg.h:261
mt8186_infracfg_ao_regs::reserved32
u32 reserved32[3]
Definition: infracfg.h:228
mt8186_infracfg_ao_regs::infra_topaxi_bus_dbg_con_a0
u32 infra_topaxi_bus_dbg_con_a0
Definition: infracfg.h:114
mt8186_infracfg_ao_regs::reserved19
u32 reserved19[24]
Definition: infracfg.h:150
mt8186_infracfg_ao_regs::module_sw_cg_2_set
u32 module_sw_cg_2_set
Definition: infracfg.h:31
mt8186_infracfg_ao_regs::reserved22
u32 reserved22[59]
Definition: infracfg.h:161
mt8186_infracfg_ao_regs::infra_ao_mcu_pwr_mask
u32 infra_ao_mcu_pwr_mask
Definition: infracfg.h:209
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_u_lnk_si0_to_infra_ip1sys_bus_asl8_axi_pwr_prot_ctrl_0
u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip1sys_bus_asl8_axi_pwr_prot_ctrl_0
Definition: infracfg.h:241
mt8186_infracfg_ao_regs::module_clk_sel
u32 module_clk_sel
Definition: infracfg.h:28
mt8186_infracfg_ao_regs::infra_mci_cg_mfg_sec_sta
u32 infra_mci_cg_mfg_sec_sta
Definition: infracfg.h:69
mt8186_infracfg_ao_regs::infra_topaxi_protecten_sta0_1
u32 infra_topaxi_protecten_sta0_1
Definition: infracfg.h:83
mt8186_infracfg_ao_regs::reserved17
u32 reserved17[3]
Definition: infracfg.h:141
mt8186_infracfg_ao_regs::infra_mci_trans_con_read
u32 infra_mci_trans_con_read
Definition: infracfg.h:78
mt8186_infracfg_ao_regs::infra_topaxi_protecten_3_set
u32 infra_topaxi_protecten_3_set
Definition: infracfg.h:108
mt8186_infracfg_ao_regs::reserved31
u32 reserved31[48]
Definition: infracfg.h:226
mt8186_infracfg_ao_regs::conn_bus_con
u32 conn_bus_con
Definition: infracfg.h:145
mt8186_infracfg_ao_regs::infra_topaxi_protecten
u32 infra_topaxi_protecten
Definition: infracfg.h:70
mt8186_infracfg_ao_regs::infrabus_dbg9
u32 infrabus_dbg9
Definition: infracfg.h:259
mt8186_infracfg_ao_regs::infra_ao_dbg_con0
u32 infra_ao_dbg_con0
Definition: infracfg.h:156
mt8186_infracfg_ao_regs::infra_axi_aslice_ctrl
u32 infra_axi_aslice_ctrl
Definition: infracfg.h:73
mt8186_infracfg_ao_regs::infra_topaxi_trans_limiter
u32 infra_topaxi_trans_limiter
Definition: infracfg.h:95
mt8186_infracfg_ao_regs::infra_ao_pmic_wrap_tx_apb_async_sta
u32 infra_ao_pmic_wrap_tx_apb_async_sta
Definition: infracfg.h:203
mt8186_infracfg_ao_regs::infra_topaxi_cbip_aslice_ctrl
u32 infra_topaxi_cbip_aslice_ctrl
Definition: infracfg.h:91
mt8186_infracfg_ao_regs::infra_ao_cksys_apb_async_sta
u32 infra_ao_cksys_apb_async_sta
Definition: infracfg.h:202
mt8186_infracfg_ao_regs::infra_ao_sec_hyp
u32 infra_ao_sec_hyp
Definition: infracfg.h:290
mt8186_infracfg_ao_regs::infra_ao_md32_rx_apb_async_sta
u32 infra_ao_md32_rx_apb_async_sta
Definition: infracfg.h:201
mt8186_infracfg_ao_regs::infra_globalcon_rst1_clr
u32 infra_globalcon_rst1_clr
Definition: infracfg.h:51
mt8186_infracfg_ao_regs::md2_bank4_map0
u32 md2_bank4_map0
Definition: infracfg.h:132
mt8186_infracfg_ao_regs::infra_globalcon_rst3_clr
u32 infra_globalcon_rst3_clr
Definition: infracfg.h:59
mt8186_infracfg_ao_regs::infra_bus_dcm_ctrl
u32 infra_bus_dcm_ctrl
Definition: infracfg.h:18
mt8186_infracfg_ao_regs::reserved33
u32 reserved33[1]
Definition: infracfg.h:232
mt8186_infracfg_ao_regs::infra_globalcon_rst2_sta
u32 infra_globalcon_rst2_sta
Definition: infracfg.h:56
mt8186_infracfg_ao_regs::infra_globalcon_rst1_set
u32 infra_globalcon_rst1_set
Definition: infracfg.h:50
mt8186_infracfg_ao_regs::p2p_rx_clk_on
u32 p2p_rx_clk_on
Definition: infracfg.h:30
mt8186_infracfg_ao_regs::infra_topaxi_protecten_3
u32 infra_topaxi_protecten_3
Definition: infracfg.h:110
mt8186_infracfg_ao_regs::infrabus_dbg13
u32 infrabus_dbg13
Definition: infracfg.h:263
mt8186_infracfg_ao_regs::infra_infra2adsp_axi_gals_debug
u32 infra_infra2adsp_axi_gals_debug
Definition: infracfg.h:219
mt8186_infracfg_ao_regs::infra_globalcon_rst1_sta
u32 infra_globalcon_rst1_sta
Definition: infracfg.h:52
mt8186_infracfg_ao_regs::infra_top_master_sideband_1
u32 infra_top_master_sideband_1
Definition: infracfg.h:101
mt8186_infracfg_ao_regs::reserved26
u32 reserved26[11]
Definition: infracfg.h:194
mt8186_infracfg_ao_regs::reserved24
u32 reserved24[89]
Definition: infracfg.h:172
mt8186_infracfg_ao_regs::md_sleep_ctrl_mask
u32 md_sleep_ctrl_mask
Definition: infracfg.h:43
mt8186_infracfg_ao_regs::peri_cci_sideband_con
u32 peri_cci_sideband_con
Definition: infracfg.h:151
mt8186_infracfg_ao_regs::infrabus_dbg10
u32 infrabus_dbg10
Definition: infracfg.h:260
mt8186_infracfg_ao_regs::dxcc_dcu_en_lock
u32 dxcc_dcu_en_lock
Definition: infracfg.h:285
mt8186_infracfg_ao_regs::module_sw_cg_3_set
u32 module_sw_cg_3_set
Definition: infracfg.h:38
mt8186_infracfg_ao_regs::c2k_sbc_key_lock
u32 c2k_sbc_key_lock
Definition: infracfg.h:193
mt8186_infracfg_ao_regs::conn_map0
u32 conn_map0
Definition: infracfg.h:142
mt8186_infracfg_ao_regs::infrabus_dbg6
u32 infrabus_dbg6
Definition: infracfg.h:256
mt8186_infracfg_ao_regs::infrabus_dbg4
u32 infrabus_dbg4
Definition: infracfg.h:254
mt8186_infracfg_ao_regs::mfg_misc_con
u32 mfg_misc_con
Definition: infracfg.h:162
mt8186_infracfg_ao_regs::infra_topaxi_protecten_set
u32 infra_topaxi_protecten_set
Definition: infracfg.h:102
mt8186_infracfg_ao_regs::infra_topaxi_protecten_sta0
u32 infra_topaxi_protecten_sta0
Definition: infracfg.h:71
mt8186_infracfg_ao_regs::infrabus_dbg2
u32 infrabus_dbg2
Definition: infracfg.h:252
mt8186_infracfg_ao_regs::mem_dcm_ctrl
u32 mem_dcm_ctrl
Definition: infracfg.h:20
mt8186_infracfg_ao_regs::md1_sbc_key6
u32 md1_sbc_key6
Definition: infracfg.h:179
mt8186_infracfg_ao_regs::reserved11
u32 reserved11[1]
Definition: infracfg.h:76
mt8186_infracfg_ao_regs::reserved34
u32 reserved34[1]
Definition: infracfg.h:240
mt8186_infracfg_ao_regs::md1_misc_lock
u32 md1_misc_lock
Definition: infracfg.h:183
mt8186_infracfg_ao_regs::mem_cg_ctrl
u32 mem_cg_ctrl
Definition: infracfg.h:29
mt8186_infracfg_ao_regs::infra_topaxi_si0_ctl
u32 infra_topaxi_si0_ctl
Definition: infracfg.h:62
mt8186_infracfg_ao_regs::md1_bank0_map1
u32 md1_bank0_map1
Definition: infracfg.h:116
mt8186_infracfg_ao_regs::scp_infra_irq_set
u32 scp_infra_irq_set
Definition: infracfg.h:215
mt8186_infracfg_ao_regs::md1_sbc_key4
u32 md1_sbc_key4
Definition: infracfg.h:177
mt8186_infracfg_ao_regs::infra_mfg_slave_gals_ctrl
u32 infra_mfg_slave_gals_ctrl
Definition: infracfg.h:98
mt8186_infracfg_ao_regs::c2k_sbc_key0
u32 c2k_sbc_key0
Definition: infracfg.h:185
mt8186_infracfg_ao_regs::infrabus_dbg16
u32 infrabus_dbg16
Definition: infracfg.h:266
mt8186_infracfg_ao_regs::c2k_sbc_key1
u32 c2k_sbc_key1
Definition: infracfg.h:186
mt8186_infracfg_ao_regs::infra_globalcon_rst2_clr
u32 infra_globalcon_rst2_clr
Definition: infracfg.h:55
mt8186_infracfg_ao_regs::infra_ao_sec_cg_con1
u32 infra_ao_sec_cg_con1
Definition: infracfg.h:281
mt8186_infracfg_ao_regs::md1_bank0_map3
u32 md1_bank0_map3
Definition: infracfg.h:118
mt8186_infracfg_ao_regs::md1_sbc_key0
u32 md1_sbc_key0
Definition: infracfg.h:173
mt8186_infracfg_ao_regs::infra_topaxi_protecten_2_set
u32 infra_topaxi_protecten_2_set
Definition: infracfg.h:106
mt8186_infracfg_ao_regs::reserved15
u32 reserved15[4]
Definition: infracfg.h:131
mt8186_infracfg_ao_regs::conn_map3
u32 conn_map3
Definition: infracfg.h:148
mt8186_infracfg_ao_regs::md2_bank4_map3
u32 md2_bank4_map3
Definition: infracfg.h:135
mt8186_infracfg_ao_regs::infra_topaxi_protecten_2
u32 infra_topaxi_protecten_2
Definition: infracfg.h:87
mt8186_infracfg_ao_regs::reserved29
u32 reserved29[48]
Definition: infracfg.h:210
mt8186_infracfg_ao_regs::conn_map4
u32 conn_map4
Definition: infracfg.h:149
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi2sbus_ctrl_0
u32 infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi2sbus_ctrl_0
Definition: infracfg.h:238
mt8186_infracfg_ao_regs::infra_ao_dbg_con2
u32 infra_ao_dbg_con2
Definition: infracfg.h:158
mt8186_infracfg_ao_regs::infra_ao_sec_cg_con3
u32 infra_ao_sec_cg_con3
Definition: infracfg.h:288
mt8186_infracfg_ao_regs::infra_ao_pmif_spmi_tx_apb_async_sta
u32 infra_ao_pmif_spmi_tx_apb_async_sta
Definition: infracfg.h:204
mt8186_infracfg_ao_regs::infra_acp
u32 infra_acp
Definition: infracfg.h:269
mt8186_infracfg_ao_regs::infra_mci_emi_trans_con
u32 infra_mci_emi_trans_con
Definition: infracfg.h:81
mt8186_infracfg_ao_regs::md2_bank4_map1
u32 md2_bank4_map1
Definition: infracfg.h:133
mt8186_infracfg_ao_regs::nna_infra_gals_ctrl
u32 nna_infra_gals_ctrl
Definition: infracfg.h:274
mt8186_infracfg_ao_regs::reserved6
u32 reserved6[5]
Definition: infracfg.h:45
mt8186_infracfg_ao_regs::infra_rsvd2
u32 infra_rsvd2
Definition: infracfg.h:167
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_u_si0_ctrl_4
u32 infra_ipsys_s_bus_u_si0_ctrl_4
Definition: infracfg.h:247
mt8186_infracfg_ao_regs::infrabus_dbg14
u32 infrabus_dbg14
Definition: infracfg.h:264
mt8186_infracfg_ao_regs::nna2_emi_axi_gals_debug
u32 nna2_emi_axi_gals_debug
Definition: infracfg.h:223
mt8186_infracfg_ao_regs::module_sw_cg_0_sta
u32 module_sw_cg_0_sta
Definition: infracfg.h:26
mt8186_infracfg_ao_regs::infrabus_dbg0
u32 infrabus_dbg0
Definition: infracfg.h:250
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_u_si0_ctrl_3
u32 infra_ipsys_s_bus_u_si0_ctrl_3
Definition: infracfg.h:246
mt8186_infracfg_ao_regs::md1_bank0_map2
u32 md1_bank0_map2
Definition: infracfg.h:117
mt8186_infracfg_ao_regs::md1_bank0_map0
u32 md1_bank0_map0
Definition: infracfg.h:115
mt8186_infracfg_ao_regs::infra_topaxi_protecten_1_set
u32 infra_topaxi_protecten_1_set
Definition: infracfg.h:104
mt8186_infracfg_ao_regs::infra_ao_md32_tx_apb_async_sta
u32 infra_ao_md32_tx_apb_async_sta
Definition: infracfg.h:200
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_u_si0_ctrl_0
u32 infra_ipsys_s_bus_u_si0_ctrl_0
Definition: infracfg.h:243
mt8186_infracfg_ao_regs::infra_mfg_master_m1_gals_ctrl
u32 infra_mfg_master_m1_gals_ctrl
Definition: infracfg.h:100
mt8186_infracfg_ao_regs::infra_mci_async_ctl
u32 infra_mci_async_ctl
Definition: infracfg.h:68
mt8186_infracfg_ao_regs::infra_mci_si1_ctl
u32 infra_mci_si1_ctl
Definition: infracfg.h:66
mt8186_infracfg_ao_regs::infra_topaxi_aslice_ctrl
u32 infra_topaxi_aslice_ctrl
Definition: infracfg.h:86
mt8186_infracfg_ao_regs::reserved10
u32 reserved10[41]
Definition: infracfg.h:61
mt8186_infracfg_ao_regs::c2k_sbc_key4
u32 c2k_sbc_key4
Definition: infracfg.h:189
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_u_lnk_si0_to_infra_ip0sys_bus_asl7_axi_pwr_prot_ctrl_0
u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip0sys_bus_asl7_axi_pwr_prot_ctrl_0
Definition: infracfg.h:239
mt8186_infracfg_ao_regs::infra_topaxi_protecten_sta0_2
u32 infra_topaxi_protecten_sta0_2
Definition: infracfg.h:88
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_bcrm_extended_bus_protect_rw_ctrl_0
u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_rw_ctrl_0
Definition: infracfg.h:235
mt8186_infracfg_ao_regs::subsys_pdn_nohang_dis1
u32 subsys_pdn_nohang_dis1
Definition: infracfg.h:197
mt8186_infracfg_ao_regs::infra_msdc_con
u32 infra_msdc_con
Definition: infracfg.h:164
mt8186_infracfg_ao_regs::c2k_sbc_key3
u32 c2k_sbc_key3
Definition: infracfg.h:188
mt8186_infracfg_ao_regs::reserved36
u32 reserved36[111]
Definition: infracfg.h:267
mt8186_infracfg_ao_regs::nn2infra_axi_gals_debug
u32 nn2infra_axi_gals_debug
Definition: infracfg.h:224
mt8186_infracfg_ao_regs::infra_topaxi_si1_ctl
u32 infra_topaxi_si1_ctl
Definition: infracfg.h:63
mt8186_infracfg_ao_regs::pll_ulposc_con0
u32 pll_ulposc_con0
Definition: infracfg.h:211
mt8186_infracfg_ao_regs::reserved12
u32 reserved12[1]
Definition: infracfg.h:85
mt8186_infracfg_ao_regs::reserved2
u32 reserved2[7]
Definition: infracfg.h:17
mt8186_infracfg_ao_regs::md2_bank4_map2
u32 md2_bank4_map2
Definition: infracfg.h:134
mt8186_infracfg_ao_regs::infra_ao_scpsys_apb_async_sta
u32 infra_ao_scpsys_apb_async_sta
Definition: infracfg.h:199
mt8186_infracfg_ao_regs::infra_ao_sec_mfg_hyp
u32 infra_ao_sec_mfg_hyp
Definition: infracfg.h:292
mt8186_infracfg_ao_regs::infra_adsp2emi_axi_gals_debug
u32 infra_adsp2emi_axi_gals_debug
Definition: infracfg.h:221
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi_pwr_prot_ctrl_0
u32 infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi_pwr_prot_ctrl_0
Definition: infracfg.h:237
mt8186_infracfg_ao_regs::md2_bank0_map0
u32 md2_bank0_map0
Definition: infracfg.h:127
mt8186_infracfg_ao_regs::infra_mci_si0_ctl
u32 infra_mci_si0_ctl
Definition: infracfg.h:65
mt8186_infracfg_ao_regs::infra_ao_sec_con
u32 infra_ao_sec_con
Definition: infracfg.h:279
mt8186_infracfg_ao_regs::md1_sbc_key3
u32 md1_sbc_key3
Definition: infracfg.h:176
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_u_si0_ctrl_2
u32 infra_ipsys_s_bus_u_si0_ctrl_2
Definition: infracfg.h:245
mt8186_infracfg_ao_regs::infra_mci_id_remap_con
u32 infra_mci_id_remap_con
Definition: infracfg.h:80
mt8186_infracfg_ao_regs::infra_topaxi_cbip_slice_ctrl
u32 infra_topaxi_cbip_slice_ctrl
Definition: infracfg.h:92
mt8186_infracfg_ao_regs::ap2md_dummy
u32 ap2md_dummy
Definition: infracfg.h:140
mt8186_infracfg_ao_regs::dramc_wbr
u32 dramc_wbr
Definition: infracfg.h:35
mt8186_infracfg_ao_regs::module_sw_cg_2_clr
u32 module_sw_cg_2_clr
Definition: infracfg.h:32
mt8186_infracfg_ao_regs::rg_ccif4_con_pwr_flag
u32 rg_ccif4_con_pwr_flag
Definition: infracfg.h:230
mt8186_infracfg_ao_regs::module_sw_cg_1_clr
u32 module_sw_cg_1_clr
Definition: infracfg.h:25
mt8186_infracfg_ao_regs::infra_ao_sec_cg_con2
u32 infra_ao_sec_cg_con2
Definition: infracfg.h:286
mt8186_infracfg_ao_regs::infrabus_dbg7
u32 infrabus_dbg7
Definition: infracfg.h:257
mt8186_infracfg_ao_regs::md1_sbc_key2
u32 md1_sbc_key2
Definition: infracfg.h:175
mt8186_infracfg_ao_regs::infra_globalcon_rst0_sta
u32 infra_globalcon_rst0_sta
Definition: infracfg.h:48
mt8186_infracfg_ao_regs::conn_map1
u32 conn_map1
Definition: infracfg.h:144
mt8186_infracfg_ao_regs::infra_mci_trans_con_write
u32 infra_mci_trans_con_write
Definition: infracfg.h:79
mt8186_infracfg_ao_regs::infra_rsvd5
u32 infra_rsvd5
Definition: infracfg.h:170
mt8186_infracfg_ao_regs::pll_ulposc_con1
u32 pll_ulposc_con1
Definition: infracfg.h:212
mt8186_infracfg_ao_regs::reserved20
u32 reserved20[2]
Definition: infracfg.h:153
mt8186_infracfg_ao_regs::pll_auxadc_con0
u32 pll_auxadc_con0
Definition: infracfg.h:214
mt8186_infracfg_ao_regs::infra_ao_sec_rst_con2
u32 infra_ao_sec_rst_con2
Definition: infracfg.h:284
mt8186_infracfg_ao_regs::infra_ao_sec_rst_con0
u32 infra_ao_sec_rst_con0
Definition: infracfg.h:282
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_u_lnk_si0_to_infra_ip2sys_bus_asl9_axi_pwr_prot_ctrl_0
u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip2sys_bus_asl9_axi_pwr_prot_ctrl_0
Definition: infracfg.h:242
mt8186_infracfg_ao_regs::infra_globalcon_rst0_set
u32 infra_globalcon_rst0_set
Definition: infracfg.h:46
mt8186_infracfg_ao_regs::md2_bank0_map2
u32 md2_bank0_map2
Definition: infracfg.h:129
mt8186_infracfg_ao_regs::i2c_dbtool_misc
u32 i2c_dbtool_misc
Definition: infracfg.h:42
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_u_si0_ctrl_1
u32 infra_ipsys_s_bus_u_si0_ctrl_1
Definition: infracfg.h:244
mt8186_infracfg_ao_regs::infra_top_master_sideband
u32 infra_top_master_sideband
Definition: infracfg.h:93
mt8186_infracfg_ao_regs::mfg_cci_sideband_con
u32 mfg_cci_sideband_con
Definition: infracfg.h:152
mt8186_infracfg_ao_regs::infra_rsvd3
u32 infra_rsvd3
Definition: infracfg.h:168
mt8186_infracfg_ao_regs::c2k_status
u32 c2k_status
Definition: infracfg.h:137
mt8186_infracfg_ao_regs::rd_ccif4_cpu_pwr_flag
u32 rd_ccif4_cpu_pwr_flag
Definition: infracfg.h:231
mt8186_infracfg_ao_regs::infra_topaxi_emi_gmc_l2c_ctrl
u32 infra_topaxi_emi_gmc_l2c_ctrl
Definition: infracfg.h:96
mt8186_infracfg_ao_regs::infra_globalcon_rst3_sta
u32 infra_globalcon_rst3_sta
Definition: infracfg.h:60
mt8186_infracfg_ao_regs::dfs_mem_dcm_ctrl
u32 dfs_mem_dcm_ctrl
Definition: infracfg.h:21
mt8186_infracfg_ao_regs::reserved8
u32 reserved8[1]
Definition: infracfg.h:53
mt8186_infracfg_ao_regs::reserved14
u32 reserved14[12]
Definition: infracfg.h:113
mt8186_infracfg_ao_regs::cldma_map0
u32 cldma_map0
Definition: infracfg.h:143
mt8186_infracfg_ao_regs::md1_bank4_map1
u32 md1_bank4_map1
Definition: infracfg.h:124
mt8186_infracfg_ao_regs::md1_misc
u32 md1_misc
Definition: infracfg.h:184
mt8186_infracfg_ao_regs::infra_topaxi_protecten_3_clr
u32 infra_topaxi_protecten_3_clr
Definition: infracfg.h:109
mt8186_infracfg_ao_regs::module_sw_cg_1_sta
u32 module_sw_cg_1_sta
Definition: infracfg.h:27
mt8186_infracfg_ao_regs::infra_ipsys_s_bus_bcrm_extended_bus_protect_ro_ctrl_0
u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_ro_ctrl_0
Definition: infracfg.h:236
mt8186_infracfg_ao_regs::infra_mci_si2_ctl
u32 infra_mci_si2_ctl
Definition: infracfg.h:67
mt8186_infracfg_ao_regs::infra_globalcon_dcmctl
u32 infra_globalcon_dcmctl
Definition: infracfg.h:16
mt8186_infracfg_ao_regs::infra_globalcon_rst0_clr
u32 infra_globalcon_rst0_clr
Definition: infracfg.h:47
mt8186_infracfg_ao_regs::infra_rsvd4
u32 infra_rsvd4
Definition: infracfg.h:169
mt8186_infracfg_ao_regs::reserved3
u32 reserved3[1]
Definition: infracfg.h:34
mt8186_infracfg_ao_regs::infra_ao_dbg_con1
u32 infra_ao_dbg_con1
Definition: infracfg.h:157
mt8186_infracfg_ao_regs::infra_ao_infra1_iommu_apb_async_sta
u32 infra_ao_infra1_iommu_apb_async_sta
Definition: infracfg.h:207
mt8186_infracfg_ao_regs::md1_bank1_map1
u32 md1_bank1_map1
Definition: infracfg.h:120
mt8186_infracfg_ao_regs::infra_rsvd1
u32 infra_rsvd1
Definition: infracfg.h:166
mt8186_infracfg_ao_regs::infra2nna_axi_gals_debug
u32 infra2nna_axi_gals_debug
Definition: infracfg.h:225
mt8186_infracfg_ao_regs::reserved1
u32 reserved1[20]
Definition: infracfg.h:15
mt8186_infracfg_ao_regs::md1_bank1_map0
u32 md1_bank1_map0
Definition: infracfg.h:119
mt8186_infracfg_ao_regs::infrabus_dbg1
u32 infrabus_dbg1
Definition: infracfg.h:251
mt8186_infracfg_ao_regs::misc_config
u32 misc_config
Definition: infracfg.h:270
mt8186_infracfg_ao_regs::c2k_sbc_key7
u32 c2k_sbc_key7
Definition: infracfg.h:192
mt8186_infracfg_ao_regs::md1_sbc_key5
u32 md1_sbc_key5
Definition: infracfg.h:178
mt8186_infracfg_ao_regs::infra_topaxi_protecten_sta1
u32 infra_topaxi_protecten_sta1
Definition: infracfg.h:72
mt8186_infracfg_ao_regs::c2k_sbc_key2
u32 c2k_sbc_key2
Definition: infracfg.h:187
mt8186_infracfg_ao_regs::reserved13
u32 reserved13[1]
Definition: infracfg.h:94
mt8186_infracfg_ao_regs::conn2infra_gals_dbg
u32 conn2infra_gals_dbg
Definition: infracfg.h:218
mt8186_infracfg_ao_regs::module_sw_cg_0_clr
u32 module_sw_cg_0_clr
Definition: infracfg.h:23
mt8186_infracfg_ao_regs::infra_topaxi_protecten_clr
u32 infra_topaxi_protecten_clr
Definition: infracfg.h:103
mt8186_infracfg_ao_regs::infra_ao_sec_rst_con1
u32 infra_ao_sec_rst_con1
Definition: infracfg.h:283
mt8186_infracfg_ao_regs::nna_emi_gals_ctrl
u32 nna_emi_gals_ctrl
Definition: infracfg.h:275
mt8186_infracfg_ao_regs::module_sw_cg_3_sta
u32 module_sw_cg_3_sta
Definition: infracfg.h:40
mt8186_infracfg_ao_regs::reserved28
u32 reserved28[6]
Definition: infracfg.h:208
mt8186_infracfg_ao_regs::infra_topaxi_protecten_1
u32 infra_topaxi_protecten_1
Definition: infracfg.h:82
mt8186_infracfg_ao_regs::infra_bonding
u32 infra_bonding
Definition: infracfg.h:195
mt8186_infracfg_ao_regs::reserved25
u32 reserved25[1]
Definition: infracfg.h:182
mt8186_infracfg_ao_regs::ddr_en_mask
u32 ddr_en_mask
Definition: infracfg.h:36
mt8186_infracfg_ao_regs::md1_sbc_key_lock
u32 md1_sbc_key_lock
Definition: infracfg.h:181
mt8186_infracfg_ao_regs::md1_sbc_key1
u32 md1_sbc_key1
Definition: infracfg.h:174
mt8186_infracfg_ao_regs::infra_adsp2infra_axi_gals_debug
u32 infra_adsp2infra_axi_gals_debug
Definition: infracfg.h:220
mt8186_infracfg_ao_regs::reserved39
u32 reserved39[2]
Definition: infracfg.h:289
mt8186_infracfg_ao_regs::module_sw_cg_1_set
u32 module_sw_cg_1_set
Definition: infracfg.h:24
mt8186_infracfg_ao_regs::md1_bank4_map0
u32 md1_bank4_map0
Definition: infracfg.h:123
mt8186_infracfg_ao_regs::subsys_pdn_nohang_dis0
u32 subsys_pdn_nohang_dis0
Definition: infracfg.h:196
mt8186_infracfg_ao_regs::infra_topaxi_mi_ctrl
u32 infra_topaxi_mi_ctrl
Definition: infracfg.h:90
mt8186_infracfg_ao_regs::reserved38
u32 reserved38[11]
Definition: infracfg.h:278
mt8186_infracfg_ao_regs::reserved9
u32 reserved9[1]
Definition: infracfg.h:57
mt8186_infracfg_ao_regs::infra_mfg_master_m0_gals_ctrl
u32 infra_mfg_master_m0_gals_ctrl
Definition: infracfg.h:99
mt8186_infracfg_ao_regs::infra_ao_dbg_con3
u32 infra_ao_dbg_con3
Definition: infracfg.h:159
mt8186_infracfg_ao_regs::md2_bank0_map1
u32 md2_bank0_map1
Definition: infracfg.h:128
mt8186_infracfg_ao_regs::infra_mcu2emi_slice
u32 infra_mcu2emi_slice
Definition: infracfg.h:291
mt8186_infracfg_ao_regs::pmicw_clock_ctrl
u32 pmicw_clock_ctrl
Definition: infracfg.h:44
mt8186_infracfg_ao_regs::md1_sbc_key7
u32 md1_sbc_key7
Definition: infracfg.h:180
mt8186_infracfg_ao_regs::c2k_spm_ctrl
u32 c2k_spm_ctrl
Definition: infracfg.h:138
mt8186_infracfg_ao_regs::infra_topaxi_protecten_2_clr
u32 infra_topaxi_protecten_2_clr
Definition: infracfg.h:107
mt8186_infracfg_ao_regs::infra_apb_async_sta
u32 infra_apb_async_sta
Definition: infracfg.h:74