coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
timer.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
device/mmio.h
>
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#include <soc/mcucfg.h>
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#include <soc/timer.h>
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void
timer_prepare
(
void
)
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{
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/* Set XGPT_IDX to 0, then the bit field of XGPT_CTL will be programmed
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* with following definition.
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*
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* [10: 8] Clock mode
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* 100: 26Mhz / 4
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* 010: 26Mhz / 2
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* 001: 26Mhz
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* [ 1: 1] Halt-on-debug enable bit
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* [ 0: 0] XGPT enable bit
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*/
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write32
(&
mt8173_mcucfg
->
xgpt_idx
, 0);
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/* Set clock mode to 13Mhz and enable XGPT */
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write32
(&
mt8173_mcucfg
->
xgpt_ctl
, (0x1 | ((26 /
GPT_MHZ
) << 8)));
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}
write32
static void write32(void *addr, uint32_t val)
Definition:
mmio.h:40
mmio.h
mt8173_mcucfg
static struct mt8173_mcucfg_regs *const mt8173_mcucfg
Definition:
mcucfg.h:92
timer_prepare
__weak void timer_prepare(void)
Definition:
timer.c:13
mt8173_mcucfg_regs::xgpt_ctl
u32 xgpt_ctl
Definition:
mcucfg.h:81
mt8173_mcucfg_regs::xgpt_idx
u32 xgpt_idx
Definition:
mcucfg.h:82
GPT_MHZ
#define GPT_MHZ
Definition:
timer_v1.h:10
src
soc
mediatek
mt8173
timer.c
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