#include <mcucfg.h>
Definition at line 8 of file mcucfg.h.
◆ aclken_div
u32 mt8173_mcucfg_regs::aclken_div |
◆ armpll_jit_ctrl
u32 mt8173_mcucfg_regs::armpll_jit_ctrl |
◆ bus_fabric_dcm_ctrl
u32 mt8173_mcucfg_regs::bus_fabric_dcm_ctrl |
◆ cci_acel_s1_ctrl
u32 mt8173_mcucfg_regs::cci_acel_s1_ctrl |
◆ cci_addrmap
u32 mt8173_mcucfg_regs::cci_addrmap |
◆ cci_clk_ctrl
u32 mt8173_mcucfg_regs::cci_clk_ctrl |
◆ cci_config
u32 mt8173_mcucfg_regs::cci_config |
◆ cci_nevntcntovfl
u32 mt8173_mcucfg_regs::cci_nevntcntovfl |
◆ cci_periphbase
u32 mt8173_mcucfg_regs::cci_periphbase |
◆ dfd_cnt_h
u32 mt8173_mcucfg_regs::dfd_cnt_h |
◆ dfd_cnt_l
u32 mt8173_mcucfg_regs::dfd_cnt_l |
◆ dfd_ctrl
u32 mt8173_mcucfg_regs::dfd_ctrl |
◆ fp_arch32
u32 mt8173_mcucfg_regs::fp_arch32 |
◆ fp_arch64_hw
u32 mt8173_mcucfg_regs::fp_arch64_hw |
◆ fp_arch64_lw
u32 mt8173_mcucfg_regs::fp_arch64_lw |
◆ int_pol_ctl
u32 mt8173_mcucfg_regs::int_pol_ctl[8] |
◆ l2c_sram_ctrl
u32 mt8173_mcucfg_regs::l2c_sram_ctrl |
◆ mcusys_config1_a
u32 mt8173_mcucfg_regs::mcusys_config1_a |
◆ mcusys_config_a
u32 mt8173_mcucfg_regs::mcusys_config_a |
◆ mcusys_dbg_mon
u32 mt8173_mcucfg_regs::mcusys_dbg_mon |
◆ mcusys_dbg_mon_sel_a
u32 mt8173_mcucfg_regs::mcusys_dbg_mon_sel_a |
◆ mcusys_gic_peribase_a
u32 mt8173_mcucfg_regs::mcusys_gic_peribase_a |
◆ mcusys_revid
u32 mt8173_mcucfg_regs::mcusys_revid |
◆ mcusys_rw_rsvd0
u32 mt8173_mcucfg_regs::mcusys_rw_rsvd0 |
◆ mcusys_rw_rsvd1
u32 mt8173_mcucfg_regs::mcusys_rw_rsvd1 |
◆ mem_delsel0
u32 mt8173_mcucfg_regs::mem_delsel0 |
◆ mem_delsel1
u32 mt8173_mcucfg_regs::mem_delsel1 |
◆ misccfg_mp0_rw_rsvd
u32 mt8173_mcucfg_regs::misccfg_mp0_rw_rsvd |
◆ misccfg_rw_rsvd
u32 mt8173_mcucfg_regs::misccfg_rw_rsvd |
◆ misccfg_sec_vio_status0
u32 mt8173_mcucfg_regs::misccfg_sec_vio_status0 |
◆ misccfg_sec_vio_status1
u32 mt8173_mcucfg_regs::misccfg_sec_vio_status1 |
◆ mp0_axi_config
u32 mt8173_mcucfg_regs::mp0_axi_config |
◆ mp0_ca7l_cache_config
u32 mt8173_mcucfg_regs::mp0_ca7l_cache_config |
◆ mp0_ca7l_cfg_dis
u32 mt8173_mcucfg_regs::mp0_ca7l_cfg_dis |
◆ mp0_ca7l_clken_ctrl
u32 mt8173_mcucfg_regs::mp0_ca7l_clken_ctrl |
◆ mp0_ca7l_dbg_pwr_ctrl
u32 mt8173_mcucfg_regs::mp0_ca7l_dbg_pwr_ctrl |
◆ mp0_ca7l_ir_mon
u32 mt8173_mcucfg_regs::mp0_ca7l_ir_mon |
◆ mp0_ca7l_misc_config
u32 mt8173_mcucfg_regs::mp0_ca7l_misc_config |
◆ mp0_ca7l_rst_ctrl
u32 mt8173_mcucfg_regs::mp0_ca7l_rst_ctrl |
◆ mp0_cache_mem_delsel0
u32 mt8173_mcucfg_regs::mp0_cache_mem_delsel0 |
◆ mp0_cache_mem_delsel1
u32 mt8173_mcucfg_regs::mp0_cache_mem_delsel1 |
struct { ... } mt8173_mcucfg_regs::mp0_cpu[4] |
struct { ... } mt8173_mcucfg_regs::mp0_dbg_core[4] |
◆ mp0_dbg_ctrl
u32 mt8173_mcucfg_regs::mp0_dbg_ctrl |
◆ mp0_dbg_flag
u32 mt8173_mcucfg_regs::mp0_dbg_flag |
◆ mp0_misc_config
u32 mt8173_mcucfg_regs::mp0_misc_config[10] |
◆ mp0_ro_rsvd
u32 mt8173_mcucfg_regs::mp0_ro_rsvd |
◆ mp0_rst_status
u32 mt8173_mcucfg_regs::mp0_rst_status |
◆ mp0_rw_rsvd0
u32 mt8173_mcucfg_regs::mp0_rw_rsvd0 |
◆ mp0_rw_rsvd1
u32 mt8173_mcucfg_regs::mp0_rw_rsvd1 |
◆ mp1_clkenm_div
u32 mt8173_mcucfg_regs::mp1_clkenm_div |
◆ mp1_config_res
u32 mt8173_mcucfg_regs::mp1_config_res |
◆ mp1_cpucfg
u32 mt8173_mcucfg_regs::mp1_cpucfg |
◆ mp1_miscdbg
u32 mt8173_mcucfg_regs::mp1_miscdbg |
◆ mp1_rst_ctl
u32 mt8173_mcucfg_regs::mp1_rst_ctl |
◆ pc_hw
u32 mt8173_mcucfg_regs::pc_hw |
◆ pc_lw
u32 mt8173_mcucfg_regs::pc_lw |
◆ pclken_div
u32 mt8173_mcucfg_regs::pclken_div |
◆ ptpod2_ctl0
u32 mt8173_mcucfg_regs::ptpod2_ctl0 |
◆ ptpod2_ctl1
u32 mt8173_mcucfg_regs::ptpod2_ctl1 |
◆ reserved0_0
u32 mt8173_mcucfg_regs::reserved0_0[100] |
◆ reserved0_1
u32 mt8173_mcucfg_regs::reserved0_1[13] |
◆ reserved0_2
u32 mt8173_mcucfg_regs::reserved0_2[7] |
◆ reserved0_3
u32 mt8173_mcucfg_regs::reserved0_3[101] |
◆ reserved1
u32 mt8173_mcucfg_regs::reserved1[22] |
◆ reserved2
u32 mt8173_mcucfg_regs::reserved2[61] |
◆ reserved3
u32 mt8173_mcucfg_regs::reserved3 |
◆ reserved4
u32 mt8173_mcucfg_regs::reserved4 |
◆ reserved5
u32 mt8173_mcucfg_regs::reserved5 |
◆ sec_range0_end
u32 mt8173_mcucfg_regs::sec_range0_end |
◆ sec_range0_start
u32 mt8173_mcucfg_regs::sec_range0_start |
◆ sec_range_enable
u32 mt8173_mcucfg_regs::sec_range_enable |
◆ sp_arch32
u32 mt8173_mcucfg_regs::sp_arch32 |
◆ sp_arch64_hw
u32 mt8173_mcucfg_regs::sp_arch64_hw |
◆ sp_arch64_lw
u32 mt8173_mcucfg_regs::sp_arch64_lw |
◆ xgpt_ctl
u32 mt8173_mcucfg_regs::xgpt_ctl |
◆ xgpt_idx
u32 mt8173_mcucfg_regs::xgpt_idx |
The documentation for this struct was generated from the following file:
- src/soc/mediatek/mt8173/include/soc/mcucfg.h