coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c File Reference
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <ec/google/chromeec/ec.h>
Include dependency graph for gpio.c:

Go to the source code of this file.

Functions

const struct soc_amd_gpiovariant_override_gpio_table (size_t *size)
 

Variables

static const struct soc_amd_gpio bid_1_gpio_set_stage_ram []
 
static const struct soc_amd_gpio vilboz_gpio_set_stage_ram []
 

Function Documentation

◆ variant_override_gpio_table()

const struct soc_amd_gpio* variant_override_gpio_table ( size_t size)

Definition at line 25 of file gpio.c.

References ARRAY_SIZE, bid_1_gpio_set_stage_ram, google_chromeec_cbi_get_board_version(), and vilboz_gpio_set_stage_ram.

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Variable Documentation

◆ bid_1_gpio_set_stage_ram

const struct soc_amd_gpio bid_1_gpio_set_stage_ram[]
static
Initial value:
= {
PAD_GPO(GPIO_89, HIGH),
PAD_GPO(GPIO_140, HIGH),
}
#define GPIO_32
Definition: gpio_ftns.h:15
#define GPIO_89
Definition: gpio.h:65
#define GPIO_140
Definition: gpio.h:87
#define PAD_NC(pin)
Definition: gpio_defs.h:263
#define PAD_GPO(pin, direction)
Definition: gpio_defs.h:220

Definition at line 1 of file gpio.c.

Referenced by variant_override_gpio_table().

◆ vilboz_gpio_set_stage_ram

const struct soc_amd_gpio vilboz_gpio_set_stage_ram[]
static
Initial value:
= {
PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY),
PAD_GPO(GPIO_89, HIGH),
}
#define PULL_NONE
Definition: buildOpts.c:72
#define GPIO_40
Definition: gpio.h:49
#define PAD_INT(pin, pull, trigger, action)
Definition: gpio_defs.h:224

Definition at line 1 of file gpio.c.

Referenced by variant_override_gpio_table().