coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ebi2.h
Go to the documentation of this file.
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/* Taken from U-Boot. */
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/* SPDX-License-Identifier: BSD-3-Clause */
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#ifndef __SOC_QUALCOMM_IPQ40XX_EBI2_H_
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#define __SOC_QUALCOMM_IPQ40XX_EBI2_H_
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#include <
stdint.h
>
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#define EBI2CR_BASE (0x1A600000)
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struct
ebi2cr_regs
{
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uint32_t
chip_select_cfg0
;
/* 0x00000000 */
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uint32_t
cfg
;
/* 0x00000004 */
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uint32_t
hw_info
;
/* 0x00000008 */
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uint8_t
reserved0
[20];
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uint32_t
lcd_cfg0
;
/* 0x00000020 */
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uint32_t
lcd_cfg1
;
/* 0x00000024 */
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uint8_t
reserved1
[8];
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uint32_t
arbiter_cfg
;
/* 0x00000030 */
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uint8_t
reserved2
[28];
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uint32_t
debug_sel
;
/* 0x00000050 */
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uint32_t
crc_cfg
;
/* 0x00000054 */
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uint32_t
crc_reminder_cfg
;
/* 0x00000058 */
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uint32_t
nand_adm_mux
;
/* 0x0000005C */
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uint32_t
mutex_addr_offset
;
/* 0x00000060 */
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uint32_t
misr_value
;
/* 0x00000064 */
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uint32_t
clkon_cfg
;
/* 0x00000068 */
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uint32_t
core_clkon_cfg
;
/* 0x0000006C */
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};
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/* Register: EBI2_CHIP_SELECT_CFG0 */
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#define CS7_CFG_MASK 0x00001000
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#define CS7_CFG_DISABLE 0x00000000
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#define CS7_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00001000
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#define CS7_CFG(i) ((i) << 12)
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#define CS6_CFG_MASK 0x00000800
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#define CS6_CFG_DISABLE 0x00000000
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#define CS6_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000800
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#define CS6_CFG(i) ((i) << 11)
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#define ETM_CS_CFG_MASK 0x00000400
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#define ETM_CS_CFG_DISABLE 0x00000000
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#define ETM_CS_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000400
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#define ETM_CS_CFG(i) ((i) << 10)
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#define CS5_CFG_MASK 0x00000300
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#define CS5_CFG_DISABLE 0x00000000
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#define CS5_CFG_LCD_DEVICE_CONNECTED 0x00000100
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#define CS5_CFG_LCD_DEVICE_CHIP_ENABLE 0x00000200
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#define CS5_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000300
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#define CS5_CFG(i) ((i) << 8)
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#define CS4_CFG_MASK 0x000000c0
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#define CS4_CFG_DISABLE 0x00000000
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#define CS4_CFG_LCD_DEVICE_CONNECTED 0x00000040
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#define CS4_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x000000C0
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#define CS4_CFG(i) ((i) << 6)
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#define CS3_CFG_MASK 0x00000020
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#define CS3_CFG_DISABLE 0x00000000
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#define CS3_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000020
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#define CS3_CFG(i) ((i) << 5)
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#define CS2_CFG_MASK 0x00000010
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#define CS2_CFG_DISABLE 0x00000000
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#define CS2_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000010
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#define CS2_CFG(i) ((i) << 4)
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#define CS1_CFG_MASK 0x0000000c
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#define CS1_CFG_DISABLE 0x00000000
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#define CS1_CFG_SERIAL_FLASH_DEVICE 0x00000004
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#define CS1_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000008
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#define CS1_CFG(i) ((i) << 2)
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#define CS0_CFG_MASK 0x00000003
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#define CS0_CFG_DISABLE 0x00000000
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#define CS0_CFG_SERIAL_FLASH_DEVICE 0x00000001
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#define CS0_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000002
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#define CS0_CFG(i) ((i) << 0)
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#endif
stdint.h
uint32_t
unsigned int uint32_t
Definition:
stdint.h:14
uint8_t
unsigned char uint8_t
Definition:
stdint.h:8
ebi2cr_regs
Definition:
ebi2.h:10
ebi2cr_regs::chip_select_cfg0
uint32_t chip_select_cfg0
Definition:
ebi2.h:11
ebi2cr_regs::arbiter_cfg
uint32_t arbiter_cfg
Definition:
ebi2.h:18
ebi2cr_regs::debug_sel
uint32_t debug_sel
Definition:
ebi2.h:20
ebi2cr_regs::misr_value
uint32_t misr_value
Definition:
ebi2.h:25
ebi2cr_regs::cfg
uint32_t cfg
Definition:
ebi2.h:12
ebi2cr_regs::clkon_cfg
uint32_t clkon_cfg
Definition:
ebi2.h:26
ebi2cr_regs::lcd_cfg0
uint32_t lcd_cfg0
Definition:
ebi2.h:15
ebi2cr_regs::reserved2
uint8_t reserved2[28]
Definition:
ebi2.h:19
ebi2cr_regs::crc_reminder_cfg
uint32_t crc_reminder_cfg
Definition:
ebi2.h:22
ebi2cr_regs::reserved0
uint8_t reserved0[20]
Definition:
ebi2.h:14
ebi2cr_regs::lcd_cfg1
uint32_t lcd_cfg1
Definition:
ebi2.h:16
ebi2cr_regs::mutex_addr_offset
uint32_t mutex_addr_offset
Definition:
ebi2.h:24
ebi2cr_regs::nand_adm_mux
uint32_t nand_adm_mux
Definition:
ebi2.h:23
ebi2cr_regs::core_clkon_cfg
uint32_t core_clkon_cfg
Definition:
ebi2.h:27
ebi2cr_regs::reserved1
uint8_t reserved1[8]
Definition:
ebi2.h:17
ebi2cr_regs::hw_info
uint32_t hw_info
Definition:
ebi2.h:13
ebi2cr_regs::crc_cfg
uint32_t crc_cfg
Definition:
ebi2.h:21
src
soc
qualcomm
ipq40xx
include
soc
ebi2.h
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