coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage_fsp_params.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <assert.h>
4 #include <fsp/api.h>
5 #include <soc/romstage.h>
6 #include <soc/meminit.h>
7 
8 static const struct mb_cfg ddr5_mem_config = {
10 
11  .rcomp = {
12  /* Baseboard uses only 100ohm Rcomp resistor */
13  .resistor = 100,
14 
15  /* Baseboard Rcomp target values */
16  .targets = { 50, 30, 30, 30, 27 },
17  },
18 
19  .ect = true, /* Early Command Training */
20 
21  .UserBd = BOARD_TYPE_MOBILE,
22 
23  .LpDdrDqDqsReTraining = 1,
24 
25  .ddr_config = {
26  .dq_pins_interleaved = false,
27  }
28 };
29 
30 void mainboard_memory_init_params(FSPM_UPD *memupd)
31 {
32  const struct mb_cfg *mem_config = &ddr5_mem_config;
33  const bool half_populated = false;
34 
35  const struct mem_spd dimm_module_spd_info = {
37  .smbus = {
38  [3] = {
39  .addr_dimm[0] = 0x52,
40  .addr_dimm[1] = 0x53,
41  },
42  },
43  };
44 
45  memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated);
46 }
void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated)
Definition: meminit.c:238
@ MEM_TYPE_DDR5
Definition: meminit.h:12
@ MEM_TOPO_DIMM_MODULE
Definition: meminit.h:26
void mainboard_memory_init_params(FSPM_UPD *memupd)
static const struct mb_cfg mem_config
Definition: memory.c:11
static const struct mb_cfg ddr5_mem_config
@ BOARD_TYPE_MOBILE
Definition: romstage.h:14
Definition: meminit.h:71
enum mem_type type
Definition: meminit.h:72
enum mem_topology topo
Definition: meminit.h:38