coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage_fsp_params.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
assert.h
>
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#include <fsp/api.h>
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#include <soc/romstage.h>
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#include <soc/meminit.h>
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static
const
struct
mb_cfg
ddr5_mem_config
= {
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.
type
=
MEM_TYPE_DDR5
,
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.rcomp = {
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/* Baseboard uses only 100ohm Rcomp resistor */
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.resistor = 100,
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/* Baseboard Rcomp target values */
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.targets = { 50, 30, 30, 30, 27 },
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},
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.ect =
true
,
/* Early Command Training */
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.UserBd =
BOARD_TYPE_MOBILE
,
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.LpDdrDqDqsReTraining = 1,
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.ddr_config = {
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.dq_pins_interleaved =
false
,
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}
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};
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void
mainboard_memory_init_params
(FSPM_UPD *memupd)
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{
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const
struct
mb_cfg
*
mem_config
= &
ddr5_mem_config
;
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const
bool
half_populated =
false
;
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const
struct
mem_spd
dimm_module_spd_info = {
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.
topo
=
MEM_TOPO_DIMM_MODULE
,
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.smbus = {
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[3] = {
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.addr_dimm[0] = 0x52,
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.addr_dimm[1] = 0x53,
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},
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},
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};
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memcfg_init
(memupd,
mem_config
, &dimm_module_spd_info, half_populated);
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}
memcfg_init
void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated)
Definition:
meminit.c:238
MEM_TYPE_DDR5
@ MEM_TYPE_DDR5
Definition:
meminit.h:12
assert.h
MEM_TOPO_DIMM_MODULE
@ MEM_TOPO_DIMM_MODULE
Definition:
meminit.h:26
mainboard_memory_init_params
void mainboard_memory_init_params(FSPM_UPD *memupd)
Definition:
romstage_fsp_params.c:45
mem_config
static const struct mb_cfg mem_config
Definition:
memory.c:11
ddr5_mem_config
static const struct mb_cfg ddr5_mem_config
Definition:
romstage_fsp_params.c:8
BOARD_TYPE_MOBILE
@ BOARD_TYPE_MOBILE
Definition:
romstage.h:14
mb_cfg
Definition:
meminit.h:71
mb_cfg::type
enum mem_type type
Definition:
meminit.h:72
mem_spd
Definition:
meminit.h:37
mem_spd::topo
enum mem_topology topo
Definition:
meminit.h:38
src
mainboard
prodrive
atlas
romstage_fsp_params.c
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