coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Macros | |
#define | PIRQ_NC 0x1f /* Not Used */ |
#define | PIRQ_A 0x00 /* INT A */ |
#define | PIRQ_B 0x01 /* INT B */ |
#define | PIRQ_C 0x02 /* INT C */ |
#define | PIRQ_D 0x03 /* INT D */ |
#define | PIRQ_E 0x04 /* INT E */ |
#define | PIRQ_F 0x05 /* INT F */ |
#define | PIRQ_G 0x06 /* INT G */ |
#define | PIRQ_H 0x07 /* INT H */ |
#define | PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */ |
#define | PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ |
#define | PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ |
#define | PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ |
#define | PIRQ_SIRQA 0x0c /* Serial IRQ INTA */ |
#define | PIRQ_SIRQB 0x0d /* Serial IRQ INTB */ |
#define | PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ |
#define | PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ |
#define | PIRQ_SCI 0x10 /* SCI IRQ */ |
#define | PIRQ_SMBUS 0x11 /* SMBUS */ |
#define | PIRQ_ASF 0x12 /* ASF */ |
#define | PIRQ_PMON 0x16 /* Performance Monitor */ |
#define | PIRQ_SD 0x17 /* SD */ |
#define | PIRQ_SDIO 0x1a /* SDIO */ |
#define | PIRQ_CIR 0x20 /* CIR, no IRQ connected */ |
#define | PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ |
#define | PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ |
#define | PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ |
#define | PIRQ_SATA 0x41 /* SATA */ |
#define | PIRQ_EMMC 0x43 /* eMMC */ |
#define | PIRQ_GPP0 0x50 /* GPPInt0 */ |
#define | PIRQ_GPP1 0x51 /* GPPInt1 */ |
#define | PIRQ_GPP2 0x52 /* GPPInt2 */ |
#define | PIRQ_GPP3 0x53 /* GPPInt3 */ |
#define | PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ |
#define | PIRQ_I2C0 0x70 /* I2C0 */ |
#define | PIRQ_I2C1 0x71 /* I2C1 */ |
#define | PIRQ_I2C2 0x72 /* I2C2 */ |
#define | PIRQ_I2C3 0x73 /* I2C3 */ |
#define | PIRQ_UART0 0x74 /* UART0 */ |
#define | PIRQ_UART1 0x75 /* UART1 */ |
#define | PIRQ_I2C4 0x76 /* I2C4 */ |
#define | PIRQ_I2C5 0x77 /* I2C5 */ |
#define | PIRQ_UART2 0x78 /* UART2 */ |
#define | PIRQ_UART3 0x79 /* UART3 */ |
#define PIRQ_A 0x00 /* INT A */ |
Definition at line 12 of file amd_pci_int_defs.h.
#define PIRQ_ASF 0x12 /* ASF */ |
Definition at line 30 of file amd_pci_int_defs.h.
#define PIRQ_B 0x01 /* INT B */ |
Definition at line 13 of file amd_pci_int_defs.h.
#define PIRQ_C 0x02 /* INT C */ |
Definition at line 14 of file amd_pci_int_defs.h.
#define PIRQ_CIR 0x20 /* CIR, no IRQ connected */ |
Definition at line 36 of file amd_pci_int_defs.h.
#define PIRQ_D 0x03 /* INT D */ |
Definition at line 15 of file amd_pci_int_defs.h.
Definition at line 16 of file amd_pci_int_defs.h.
#define PIRQ_EMMC 0x43 /* eMMC */ |
Definition at line 43 of file amd_pci_int_defs.h.
#define PIRQ_F 0x05 /* INT F */ |
Definition at line 17 of file amd_pci_int_defs.h.
#define PIRQ_G 0x06 /* INT G */ |
Definition at line 18 of file amd_pci_int_defs.h.
#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ |
Definition at line 50 of file amd_pci_int_defs.h.
#define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ |
Definition at line 37 of file amd_pci_int_defs.h.
#define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ |
Definition at line 38 of file amd_pci_int_defs.h.
#define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ |
Definition at line 39 of file amd_pci_int_defs.h.
#define PIRQ_GPP0 0x50 /* GPPInt0 */ |
Definition at line 45 of file amd_pci_int_defs.h.
#define PIRQ_GPP1 0x51 /* GPPInt1 */ |
Definition at line 46 of file amd_pci_int_defs.h.
#define PIRQ_GPP2 0x52 /* GPPInt2 */ |
Definition at line 47 of file amd_pci_int_defs.h.
#define PIRQ_GPP3 0x53 /* GPPInt3 */ |
Definition at line 48 of file amd_pci_int_defs.h.
#define PIRQ_H 0x07 /* INT H */ |
Definition at line 19 of file amd_pci_int_defs.h.
#define PIRQ_I2C0 0x70 /* I2C0 */ |
Definition at line 52 of file amd_pci_int_defs.h.
#define PIRQ_I2C1 0x71 /* I2C1 */ |
Definition at line 53 of file amd_pci_int_defs.h.
#define PIRQ_I2C2 0x72 /* I2C2 */ |
Definition at line 54 of file amd_pci_int_defs.h.
#define PIRQ_I2C3 0x73 /* I2C3 */ |
Definition at line 55 of file amd_pci_int_defs.h.
#define PIRQ_I2C4 0x76 /* I2C4 */ |
Definition at line 58 of file amd_pci_int_defs.h.
#define PIRQ_I2C5 0x77 /* I2C5 */ |
Definition at line 59 of file amd_pci_int_defs.h.
#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */ |
Definition at line 20 of file amd_pci_int_defs.h.
#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ |
Definition at line 21 of file amd_pci_int_defs.h.
#define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ |
Definition at line 22 of file amd_pci_int_defs.h.
#define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ |
Definition at line 23 of file amd_pci_int_defs.h.
#define PIRQ_NC 0x1f /* Not Used */ |
Definition at line 11 of file amd_pci_int_defs.h.
#define PIRQ_PMON 0x16 /* Performance Monitor */ |
Definition at line 32 of file amd_pci_int_defs.h.
#define PIRQ_SATA 0x41 /* SATA */ |
Definition at line 41 of file amd_pci_int_defs.h.
#define PIRQ_SCI 0x10 /* SCI IRQ */ |
Definition at line 28 of file amd_pci_int_defs.h.
#define PIRQ_SD 0x17 /* SD */ |
Definition at line 33 of file amd_pci_int_defs.h.
#define PIRQ_SDIO 0x1a /* SDIO */ |
Definition at line 34 of file amd_pci_int_defs.h.
#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */ |
Definition at line 24 of file amd_pci_int_defs.h.
#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */ |
Definition at line 25 of file amd_pci_int_defs.h.
#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ |
Definition at line 26 of file amd_pci_int_defs.h.
#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ |
Definition at line 27 of file amd_pci_int_defs.h.
#define PIRQ_SMBUS 0x11 /* SMBUS */ |
Definition at line 29 of file amd_pci_int_defs.h.
#define PIRQ_UART0 0x74 /* UART0 */ |
Definition at line 56 of file amd_pci_int_defs.h.
#define PIRQ_UART1 0x75 /* UART1 */ |
Definition at line 57 of file amd_pci_int_defs.h.
#define PIRQ_UART2 0x78 /* UART2 */ |
Definition at line 60 of file amd_pci_int_defs.h.
#define PIRQ_UART3 0x79 /* UART3 */ |
Definition at line 61 of file amd_pci_int_defs.h.