3 #ifndef __SOC_MEDIATEK_MT8173_MT6391_H__
4 #define __SOC_MEDIATEK_MT8173_MT6391_H__
@ MT6391_GPIO_PULLSEL_BASE
@ MT6391_GPIO_PULLEN_BASE
@ PMIC_RG_DCXO_LDO_BB_V_SHIFT
@ PMIC_RG_DCXO_ATTEN_BB_SHIFT
@ PMIC_RG_DCXO_MANUAL_SYNC_EN_SHIFT
@ PMIC_RG_DCXO_MANUAL_SYNC_EN_MASK
@ PMIC_RG_DCXO_MANUAL_C1C2_SYNC_EN_SHIFT
@ PMIC_RG_DCXO_C2_UNTRIM_MASK
@ PMIC_RG_DCXO_ATTEN_BB_MASK
@ PMIC_RG_DCXO_LDO_BB_V_MASK
@ PMIC_RG_DCXO_C2_UNTRIM_SHIFT
@ PMIC_RG_DCXO_MANUAL_C1C2_SYNC_EN_MASK
@ PMIC_RG_VCAMA_VOSEL_SHIFT
@ PMIC_RG_VCAMA_VOSEL_MASK
void mt6391_enable_reset_when_ap_resets(void)
void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
void mt6391_gpio_set_pull(u32 gpio, enum mt6391_pull_enable enable, enum mt6391_pull_select select)
@ PMIC_RG_SYSRSTB_EN_MASK
@ PMIC_RG_PWRKEY_DEB_SHIFT
@ PMIC_RG_AP_RST_DIS_SHIFT
@ PMIC_RG_STRUP_MAN_RST_EN_MASK
@ PMIC_RG_TOP_RST_MISC_RSV_3_SHIFT
@ PMIC_RG_SYSRSTB_EN_SHIFT
@ PMIC_RG_RST_PART_SEL_SHIFT
@ PMIC_RG_TOP_RST_MISC_RSV_3_MASK
@ PMIC_RG_AP_RST_DIS_MASK
@ PMIC_RG_STRUP_MAN_RST_EN_SHIFT
@ PMIC_RG_RST_PART_SEL_MASK
@ PMIC_RG_HOMEKEY_DEB_MASK
@ PMIC_RG_HOMEKEY_DEB_SHIFT
@ PMIC_RG_PWRKEY_DEB_MASK
@ PMIC_RG_FQMTR_PDN_SHIFT
void mt6391_gpio_input_pullup(u32 gpio)
void mt6391_gpio_set_mode(u32 gpio, int mode)
int mt6391_configure_ca53_voltage(int uv)
@ MT6391_GPIO_PULL_ENABLE
@ MT6391_GPIO_PULL_DISABLE
@ PMIC_RG_EFUSE_DOUT_304_319
@ PMIC_RG_EFUSE_DOUT_256_271
@ PMIC_RG_EFUSE_DOUT_288_303
@ PMIC_RG_EFUSE_DOUT_272_287
void mt6391_gpio_set(u32 gpio, int value)
void mt6391_gpio_output(u32 gpio, int value)
int mt6391_gpio_get(u32 gpio)
void mt6391_gpio_input(u32 gpio)
void mt6391_gpio_input_pulldown(u32 gpio)
@ PMIC_RG_DCXO_MANUAL_CON1
@ PMIC_RG_DCXO_FORCE_MODE1
@ PMIC_RG_DCXO_ANALOG_CON1
@ PMIC_RG_PMIC_RG_RG_DCXO_CON0