|
| enum | {
POWER_PARTID_CRAIL = 0
, POWER_PARTID_TD = 1
, POWER_PARTID_VE = 2
, POWER_PARTID_PCX = 3
,
POWER_PARTID_C0L2 = 5
, POWER_PARTID_MPE = 6
, POWER_PARTID_HEG = 7
, POWER_PARTID_SAX = 8
,
POWER_PARTID_CE1 = 9
, POWER_PARTID_CE2 = 10
, POWER_PARTID_CE3 = 11
, POWER_PARTID_CELP = 12
,
POWER_PARTID_CE0 = 14
, POWER_PARTID_C0NC = 15
, POWER_PARTID_C1NC = 16
, POWER_PARTID_SOR = 17
,
POWER_PARTID_DIS = 18
, POWER_PARTID_DISB = 19
, POWER_PARTID_XUSBA = 20
, POWER_PARTID_XUSBB = 21
,
POWER_PARTID_XUSBC = 22
, POWER_PARTID_VIC = 23
, POWER_PARTID_IRAM = 24
, POWER_PARTID_NVDEC = 25
,
POWER_PARTID_NVJPG = 26
, POWER_PARTID_APE = 27
, POWER_PARTID_DFD = 28
, POWER_PARTID_VE2 = 29
} |
| |
| enum | {
PMC_RST_STATUS_SOURCE_MASK = 0x7
, PMC_RST_STATUS_SOURCE_POR = 0x0
, PMC_RST_STATUS_SOURCE_WATCHDOG = 0x1
, PMC_RST_STATUS_SOURCE_SENSOR = 0x2
,
PMC_RST_STATUS_SOURCE_SW_MAIN = 0x3
, PMC_RST_STATUS_SOURCE_LP0 = 0x4
, PMC_RST_STATUS_NUM_SOURCES = 0x5
} |
| |
| enum | { PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f
, PMC_PWRGATE_TOGGLE_PARTID_SHIFT = 0
, PMC_PWRGATE_TOGGLE_START = 0x1 << 8
} |
| |
| enum | {
PMC_CNTRL_KBC_CLK_DIS = 0x1 << 0
, PMC_CNTRL_RTC_CLK_DIS = 0x1 << 1
, PMC_CNTRL_RTC_RST = 0x1 << 2
, PMC_CNTRL_KBC_RST = 0x1 << 3
,
PMC_CNTRL_MAIN_RST = 0x1 << 4
, PMC_CNTRL_LATCHWAKE_EN = 0x1 << 5
, PMC_CNTRL_GLITCHDET_DIS = 0x1 << 6
, PMC_CNTRL_BLINK_EN = 0x1 << 7
,
PMC_CNTRL_PWRREQ_POLARITY = 0x1 << 8
, PMC_CNTRL_PWRREQ_OE = 0x1 << 9
, PMC_CNTRL_SYSCLK_POLARITY = 0x1 << 10
, PMC_CNTRL_SYSCLK_OE = 0x1 << 11
,
PMC_CNTRL_PWRGATE_DIS = 0x1 << 12
, PMC_CNTRL_AOINIT = 0x1 << 13
, PMC_CNTRL_SIDE_EFFECT_LP0 = 0x1 << 14
, PMC_CNTRL_CPUPWRREQ_POLARITY = 0x1 << 15
,
PMC_CNTRL_CPUPWRREQ_OE = 0x1 << 16
, PMC_CNTRL_INTR_POLARITY = 0x1 << 17
, PMC_CNTRL_FUSE_OVERRIDE = 0x1 << 18
, PMC_CNTRL_CPUPWRGOOD_EN = 0x1 << 19
,
PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT = 20
, PMC_CNTRL_CPUPWRGOOD_SEL_MASK
} |
| |
| enum | { PMC_DDR_PWR_EMMC_MASK = 1 << 1
, PMC_DDR_PWR_VAL_MASK = 1 << 0
} |
| |
| enum | { PMC_DDR_CFG_PKG_MASK = 1 << 0
, PMC_DDR_CFG_IF_MASK = 1 << 1
, PMC_DDR_CFG_XM0_RESET_TRI_MASK = 1 << 12
, PMC_DDR_CFG_XM0_RESET_DPDIO_MASK = 1 << 13
} |
| |
| enum | { PMC_NO_IOPOWER_MEM_MASK = 1 << 7
, PMC_NO_IOPOWER_MEM_COMP_MASK = 1 << 16
} |
| |
| enum | { PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK = 1 << 0
, PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK = 1 << 1
, PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK = 1 << 31
} |
| |
| enum | { PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12
} |
| |
| enum | { PMC_OSC_EDPD_OVER_XOFS_SHIFT = 1
, PMC_OSC_EDPD_OVER_XOFS_MASK
} |
| |
| enum | { PMC_CMD_HOLD_LOW_BR00_11_MASK = 0x0007FF80
, DPD_OFF = 1 << 30
, DPD_ON = 2 << 30
} |
| |
| enum | {
PMC_GPIO_RAIL_AO_SHIFT = 21
, PMC_GPIO_RAIL_AO_MASK = (1 << PMC_GPIO_RAIL_AO_SHIFT)
, PMC_GPIO_RAIL_AO_DISABLE = (0 << PMC_GPIO_RAIL_AO_SHIFT)
, PMC_GPIO_RAIL_AO_ENABLE = (1 << PMC_GPIO_RAIL_AO_SHIFT)
,
PMC_AUDIO_RAIL_AO_SHIFT = 18
, PMC_AUDIO_RAIL_AO_MASK = (1 << PMC_AUDIO_RAIL_AO_SHIFT)
, PMC_AUDIO_RAIL_AO_DISABLE = (0 << PMC_AUDIO_RAIL_AO_SHIFT)
, PMC_AUDIO_RAIL_AO_ENABLE = (1 << PMC_AUDIO_RAIL_AO_SHIFT)
,
PMC_SDMMC3_RAIL_AO_SHIFT = 13
, PMC_SDMMC3_RAIL_AO_MASK = (1 << PMC_SDMMC3_RAIL_AO_SHIFT)
, PMC_SDMMC3_RAIL_AO_DISABLE = (0 << PMC_SDMMC3_RAIL_AO_SHIFT)
, PMC_SDMMC3_RAIL_AO_ENABLE = (1 << PMC_SDMMC3_RAIL_AO_SHIFT)
} |
| |
1.9.1