coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Macros | Functions
ec.h File Reference
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Macros

#define ITE_FIXED_ADDR   0x4e
 
#define NUVOTON_FIXED_ADDR   0x4e
 
#define ITE_SP1   0x01 /* Serial Port 1 (UART) */
 
#define ITE_SP2   0x02 /* Serial Port 2 (UART) */
 
#define ITE_SWUC   0x04 /* System Wake-Up Control (SWUC) */
 
#define ITE_KBCM   0x05 /* KBC / Mouse Interface */
 
#define ITE_KBCK   0x06 /* KBC / Keyboard Interface */
 
#define ITE_IR   0x0a /* Consumer IR (CIR) */
 
#define ITE_SMFI   0x0f /* Shared Memory / Flash Interface (SMFI) */
 
#define ITE_RTCT   0x10 /* RTC-like Timer (RCTC) */
 
#define ITE_PMC1   0x11 /* Power Management I/F Channel 1 (PMC1) */
 
#define ITE_PMC2   0x12 /* Power Management I/F Channel 2 (PMC2) */
 
#define ITE_SSPI   0x13 /* Serial Peripheral Interface (SSPI) */
 
#define ITE_PECI   0x14 /* Platform Environment Control Interface (PECI) */
 
#define ITE_PMC3   0x17 /* Power Management I/F Channel 3 (PMC3) */
 
#define ITE_PMC4   0x18 /* Power Management I/F Channel 4 (PMC4) */
 
#define ITE_PMC5   0x19 /* Power Management I/F Channel 5 (PMC5) */
 
#define NUVOTON_MSWC   0x04 /* Mobile System Wake-Up Control (MSWC) */
 
#define NUVOTON_KBCM   0x05 /* KBC / Mouse Interface */
 
#define NUVOTON_KBCK   0x06 /* KBC / Keyboard Interface */
 
#define NUVOTON_SHM   0x0f /* Shared Memory (SHM) */
 
#define NUVOTON_PM1   0x11 /* Power Management I/F Channel 1 (PM1) */
 
#define NUVOTON_PM2   0x12 /* Power Management I/F Channel 2 (PM2) */
 
#define NUVOTON_PM3   0x17 /* Power Management I/F Channel 3 (PM3) */
 
#define NUVOTON_ESHM   0x1d /* Extended Shared Memory (ESHM) */
 
#define NUVOTON_PM4   0x1e /* Power Management I/F Channel 3 (PM4) */
 
#define ITE_CHIPID1   0x20 /* Device ID register 1 */
 
#define ITE_CHIPID2   0x21 /* Device ID register 2 */
 
#define NUVOTON_CHIPID   0x27 /* Device ID register */
 
#define ECRAM_MAJOR_VERSION   0x00
 
#define ECRAM_MINOR_VERSION   0x01
 
#define SEC_30   0x00
 
#define MIN_1   0x01
 
#define MIN_3   0x02
 
#define MIN_5   0x03
 
#define NEVER   0x04
 
#define FN_CTRL   0x00
 
#define CTRL_FN   0x01
 
#define CHARGE_100   0x00
 
#define CHARGE_80   0xbb
 
#define CHARGE_60   0xaa
 
#define FAN_NORMAL   0x00
 
#define FAN_AGGRESSIVE   0xbb
 
#define FAN_QUIET   0xaa
 
#define UNLOCKED   0x00
 
#define LOCKED   0x01
 
#define TRACKPAD_ENABLED   0x00
 
#define TRACKPAD_DISABLED   0x22
 
#define KBL_ON   0xdd
 
#define KBL_OFF   0xcc
 
#define KBL_LOW   0xbb
 
#define KBL_HIGH   0xaa
 
#define KBL_DISABLED   0x00
 
#define KBL_ENABLED   0xdd
 

Functions

uint16_t ec_get_version (void)
 

Macro Definition Documentation

◆ CHARGE_100

#define CHARGE_100   0x00

Definition at line 70 of file ec.h.

◆ CHARGE_60

#define CHARGE_60   0xaa

Definition at line 72 of file ec.h.

◆ CHARGE_80

#define CHARGE_80   0xbb

Definition at line 71 of file ec.h.

◆ CTRL_FN

#define CTRL_FN   0x01

Definition at line 67 of file ec.h.

◆ ECRAM_MAJOR_VERSION

#define ECRAM_MAJOR_VERSION   0x00

Definition at line 51 of file ec.h.

◆ ECRAM_MINOR_VERSION

#define ECRAM_MINOR_VERSION   0x01

Definition at line 52 of file ec.h.

◆ FAN_AGGRESSIVE

#define FAN_AGGRESSIVE   0xbb

Definition at line 76 of file ec.h.

◆ FAN_NORMAL

#define FAN_NORMAL   0x00

Definition at line 75 of file ec.h.

◆ FAN_QUIET

#define FAN_QUIET   0xaa

Definition at line 77 of file ec.h.

◆ FN_CTRL

#define FN_CTRL   0x00

Definition at line 66 of file ec.h.

◆ ITE_CHIPID1

#define ITE_CHIPID1   0x20 /* Device ID register 1 */

Definition at line 46 of file ec.h.

◆ ITE_CHIPID2

#define ITE_CHIPID2   0x21 /* Device ID register 2 */

Definition at line 47 of file ec.h.

◆ ITE_FIXED_ADDR

#define ITE_FIXED_ADDR   0x4e

Definition at line 14 of file ec.h.

◆ ITE_IR

#define ITE_IR   0x0a /* Consumer IR (CIR) */

Definition at line 23 of file ec.h.

◆ ITE_KBCK

#define ITE_KBCK   0x06 /* KBC / Keyboard Interface */

Definition at line 22 of file ec.h.

◆ ITE_KBCM

#define ITE_KBCM   0x05 /* KBC / Mouse Interface */

Definition at line 21 of file ec.h.

◆ ITE_PECI

#define ITE_PECI   0x14 /* Platform Environment Control Interface (PECI) */

Definition at line 29 of file ec.h.

◆ ITE_PMC1

#define ITE_PMC1   0x11 /* Power Management I/F Channel 1 (PMC1) */

Definition at line 26 of file ec.h.

◆ ITE_PMC2

#define ITE_PMC2   0x12 /* Power Management I/F Channel 2 (PMC2) */

Definition at line 27 of file ec.h.

◆ ITE_PMC3

#define ITE_PMC3   0x17 /* Power Management I/F Channel 3 (PMC3) */

Definition at line 30 of file ec.h.

◆ ITE_PMC4

#define ITE_PMC4   0x18 /* Power Management I/F Channel 4 (PMC4) */

Definition at line 31 of file ec.h.

◆ ITE_PMC5

#define ITE_PMC5   0x19 /* Power Management I/F Channel 5 (PMC5) */

Definition at line 32 of file ec.h.

◆ ITE_RTCT

#define ITE_RTCT   0x10 /* RTC-like Timer (RCTC) */

Definition at line 25 of file ec.h.

◆ ITE_SMFI

#define ITE_SMFI   0x0f /* Shared Memory / Flash Interface (SMFI) */

Definition at line 24 of file ec.h.

◆ ITE_SP1

#define ITE_SP1   0x01 /* Serial Port 1 (UART) */

Definition at line 18 of file ec.h.

◆ ITE_SP2

#define ITE_SP2   0x02 /* Serial Port 2 (UART) */

Definition at line 19 of file ec.h.

◆ ITE_SSPI

#define ITE_SSPI   0x13 /* Serial Peripheral Interface (SSPI) */

Definition at line 28 of file ec.h.

◆ ITE_SWUC

#define ITE_SWUC   0x04 /* System Wake-Up Control (SWUC) */

Definition at line 20 of file ec.h.

◆ KBL_DISABLED

#define KBL_DISABLED   0x00

Definition at line 94 of file ec.h.

◆ KBL_ENABLED

#define KBL_ENABLED   0xdd

Definition at line 95 of file ec.h.

◆ KBL_HIGH

#define KBL_HIGH   0xaa

Definition at line 91 of file ec.h.

◆ KBL_LOW

#define KBL_LOW   0xbb

Definition at line 90 of file ec.h.

◆ KBL_OFF

#define KBL_OFF   0xcc

Definition at line 89 of file ec.h.

◆ KBL_ON

#define KBL_ON   0xdd

Definition at line 88 of file ec.h.

◆ LOCKED

#define LOCKED   0x01

Definition at line 81 of file ec.h.

◆ MIN_1

#define MIN_1   0x01

Definition at line 60 of file ec.h.

◆ MIN_3

#define MIN_3   0x02

Definition at line 61 of file ec.h.

◆ MIN_5

#define MIN_5   0x03

Definition at line 62 of file ec.h.

◆ NEVER

#define NEVER   0x04

Definition at line 63 of file ec.h.

◆ NUVOTON_CHIPID

#define NUVOTON_CHIPID   0x27 /* Device ID register */

Definition at line 48 of file ec.h.

◆ NUVOTON_ESHM

#define NUVOTON_ESHM   0x1d /* Extended Shared Memory (ESHM) */

Definition at line 42 of file ec.h.

◆ NUVOTON_FIXED_ADDR

#define NUVOTON_FIXED_ADDR   0x4e

Definition at line 15 of file ec.h.

◆ NUVOTON_KBCK

#define NUVOTON_KBCK   0x06 /* KBC / Keyboard Interface */

Definition at line 37 of file ec.h.

◆ NUVOTON_KBCM

#define NUVOTON_KBCM   0x05 /* KBC / Mouse Interface */

Definition at line 36 of file ec.h.

◆ NUVOTON_MSWC

#define NUVOTON_MSWC   0x04 /* Mobile System Wake-Up Control (MSWC) */

Definition at line 35 of file ec.h.

◆ NUVOTON_PM1

#define NUVOTON_PM1   0x11 /* Power Management I/F Channel 1 (PM1) */

Definition at line 39 of file ec.h.

◆ NUVOTON_PM2

#define NUVOTON_PM2   0x12 /* Power Management I/F Channel 2 (PM2) */

Definition at line 40 of file ec.h.

◆ NUVOTON_PM3

#define NUVOTON_PM3   0x17 /* Power Management I/F Channel 3 (PM3) */

Definition at line 41 of file ec.h.

◆ NUVOTON_PM4

#define NUVOTON_PM4   0x1e /* Power Management I/F Channel 3 (PM4) */

Definition at line 43 of file ec.h.

◆ NUVOTON_SHM

#define NUVOTON_SHM   0x0f /* Shared Memory (SHM) */

Definition at line 38 of file ec.h.

◆ SEC_30

#define SEC_30   0x00

Definition at line 59 of file ec.h.

◆ TRACKPAD_DISABLED

#define TRACKPAD_DISABLED   0x22

Definition at line 85 of file ec.h.

◆ TRACKPAD_ENABLED

#define TRACKPAD_ENABLED   0x00

Definition at line 84 of file ec.h.

◆ UNLOCKED

#define UNLOCKED   0x00

Definition at line 80 of file ec.h.

Function Documentation

◆ ec_get_version()

uint16_t ec_get_version ( void  )

Definition at line 13 of file ite.c.

References ec_read(), ECRAM_MAJOR_VERSION, and ECRAM_MINOR_VERSION.

Referenced by smbios_ec_revision().

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