coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <gpio.h>
6 #include <soc/gpio.h>
8 
10  /* DMIC_SEL */
11  PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic
12  /* USB_OC4_L - USB_A1 */
13  PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE),
14  /* USB_OC2_L - USB A0 */
15  PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE),
16  /* EN_PWR_WIFI */
17  PAD_GPO(GPIO_29, HIGH),
18  /* EN_PWR_TOUCHPAD_PS2 */
19  PAD_GPO(GPIO_67, HIGH),
20  /* DMIC_AD_EN */
21  PAD_GPO(GPIO_84, HIGH),
22  /* MST_GPIO_2 (Fw Update HDMI hub) */
24  /* EN_DEV_BEEP_L */
25  PAD_GPO(GPIO_89, HIGH),
26  /* MST_GPIO_3 (Fw Update HDMI hub) */
28  /* USI_RESET */
29  PAD_GPO(GPIO_140, HIGH),
30 };
31 
32 static const struct soc_amd_gpio trembyle_bid3_gpio_set_stage_ram[] = {
33  /* DMIC_SEL */
34  PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic
35  /* USB_OC4_L - USB_A1 */
36  PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE),
37  /* USB_OC2_L - USB A0 */
38  PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE),
39  /* EN_PWR_WIFI */
40  PAD_GPO(GPIO_29, HIGH),
41  /* EN_PWR_TOUCHPAD_PS2 */
42  PAD_GPO(GPIO_67, HIGH),
43  /* MST_GPIO_2 (Fw Update HDMI hub) */
45  /* EN_DEV_BEEP_L */
46  PAD_GPO(GPIO_89, HIGH),
47  /* MST_GPIO_3 (Fw Update HDMI hub) */
49  /* USI_RESET */
50  PAD_GPO(GPIO_140, HIGH),
51 };
52 
53 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
54 {
55  uint32_t board_version;
56 
57  /*
58  * If board version cannot be read, assume that this is an older revision of the board
59  * and so apply overrides. If board version is provided by the EC, then apply overrides
60  * if version < 2.
61  */
62  if (google_chromeec_cbi_get_board_version(&board_version) != 0)
63  board_version = 1;
64 
65  if (board_version <= 2) {
68  } else if (board_version <= 3) {
71  }
72 
73  *size = 0;
74  return NULL;
75 }
#define GPIO_18
Definition: gpio_ftns.h:17
#define ARRAY_SIZE(a)
Definition: helpers.h:12
int google_chromeec_cbi_get_board_version(uint32_t *version)
Definition: ec.c:870
#define PULL_NONE
Definition: buildOpts.c:72
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition: gpio.c:450
static const struct soc_amd_gpio trembyle_bid3_gpio_set_stage_ram[]
Definition: gpio.c:32
static const struct soc_amd_gpio trembyle_bid1_bid2_gpio_set_stage_ram[]
Definition: gpio.c:9
#define GPIO_90
Definition: gpio.h:66
#define GPIO_89
Definition: gpio.h:65
#define GPIO_84
Definition: gpio.h:60
#define GPIO_67
Definition: gpio.h:53
#define GPIO_140
Definition: gpio.h:87
#define GPIO_29
Definition: gpio.h:45
#define GPIO_86
Definition: gpio.h:62
#define PAD_GPO(pin, direction)
Definition: gpio_defs.h:220
#define PAD_NF(pin, func, pull)
Definition: gpio_defs.h:208
#define PAD_GPI(pin, pull)
Definition: gpio_defs.h:216
#define GPIO_14
Definition: gpio.h:35
#define GPIO_13
Definition: gpio.h:34
#define NULL
Definition: stddef.h:19
unsigned int uint32_t
Definition: stdint.h:14