coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <
ec/google/chromeec/ec.h
>
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static
const
struct
soc_amd_gpio
trembyle_bid1_bid2_gpio_set_stage_ram
[] = {
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/* DMIC_SEL */
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PAD_GPO
(
GPIO_13
, LOW),
// Select Camera 1 Dmic
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/* USB_OC4_L - USB_A1 */
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PAD_NF
(
GPIO_14
, USB_OC4_L,
PULL_NONE
),
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/* USB_OC2_L - USB A0 */
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PAD_NF
(
GPIO_18
, USB_OC2_L,
PULL_NONE
),
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/* EN_PWR_WIFI */
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PAD_GPO
(
GPIO_29
, HIGH),
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/* EN_PWR_TOUCHPAD_PS2 */
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PAD_GPO
(
GPIO_67
, HIGH),
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/* DMIC_AD_EN */
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PAD_GPO
(
GPIO_84
, HIGH),
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/* MST_GPIO_2 (Fw Update HDMI hub) */
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PAD_GPI
(
GPIO_86
,
PULL_NONE
),
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/* EN_DEV_BEEP_L */
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PAD_GPO
(
GPIO_89
, HIGH),
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/* MST_GPIO_3 (Fw Update HDMI hub) */
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PAD_GPI
(
GPIO_90
,
PULL_NONE
),
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/* USI_RESET */
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PAD_GPO
(
GPIO_140
, HIGH),
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};
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static
const
struct
soc_amd_gpio
trembyle_bid3_gpio_set_stage_ram
[] = {
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/* DMIC_SEL */
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PAD_GPO
(
GPIO_13
, LOW),
// Select Camera 1 Dmic
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/* USB_OC4_L - USB_A1 */
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PAD_NF
(
GPIO_14
, USB_OC4_L,
PULL_NONE
),
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/* USB_OC2_L - USB A0 */
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PAD_NF
(
GPIO_18
, USB_OC2_L,
PULL_NONE
),
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/* EN_PWR_WIFI */
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PAD_GPO
(
GPIO_29
, HIGH),
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/* EN_PWR_TOUCHPAD_PS2 */
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PAD_GPO
(
GPIO_67
, HIGH),
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/* MST_GPIO_2 (Fw Update HDMI hub) */
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PAD_GPI
(
GPIO_86
,
PULL_NONE
),
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/* EN_DEV_BEEP_L */
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PAD_GPO
(
GPIO_89
, HIGH),
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/* MST_GPIO_3 (Fw Update HDMI hub) */
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PAD_GPI
(
GPIO_90
,
PULL_NONE
),
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/* USI_RESET */
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PAD_GPO
(
GPIO_140
, HIGH),
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};
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const
struct
soc_amd_gpio
*
variant_override_gpio_table
(
size_t
*size)
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{
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uint32_t
board_version;
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/*
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* If board version cannot be read, assume that this is an older revision of the board
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* and so apply overrides. If board version is provided by the EC, then apply overrides
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* if version < 2.
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*/
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if
(
google_chromeec_cbi_get_board_version
(&board_version) != 0)
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board_version = 1;
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if
(board_version <= 2) {
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*size =
ARRAY_SIZE
(
trembyle_bid1_bid2_gpio_set_stage_ram
);
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return
trembyle_bid1_bid2_gpio_set_stage_ram
;
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}
else
if
(board_version <= 3) {
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*size =
ARRAY_SIZE
(
trembyle_bid3_gpio_set_stage_ram
);
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return
trembyle_bid3_gpio_set_stage_ram
;
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}
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*size = 0;
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return
NULL
;
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}
GPIO_18
#define GPIO_18
Definition:
gpio_ftns.h:17
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
google_chromeec_cbi_get_board_version
int google_chromeec_cbi_get_board_version(uint32_t *version)
Definition:
ec.c:870
ec.h
PULL_NONE
#define PULL_NONE
Definition:
buildOpts.c:72
variant_override_gpio_table
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition:
gpio.c:450
trembyle_bid3_gpio_set_stage_ram
static const struct soc_amd_gpio trembyle_bid3_gpio_set_stage_ram[]
Definition:
gpio.c:32
trembyle_bid1_bid2_gpio_set_stage_ram
static const struct soc_amd_gpio trembyle_bid1_bid2_gpio_set_stage_ram[]
Definition:
gpio.c:9
GPIO_90
#define GPIO_90
Definition:
gpio.h:66
GPIO_89
#define GPIO_89
Definition:
gpio.h:65
GPIO_84
#define GPIO_84
Definition:
gpio.h:60
GPIO_67
#define GPIO_67
Definition:
gpio.h:53
GPIO_140
#define GPIO_140
Definition:
gpio.h:87
GPIO_29
#define GPIO_29
Definition:
gpio.h:45
GPIO_86
#define GPIO_86
Definition:
gpio.h:62
PAD_GPO
#define PAD_GPO(pin, direction)
Definition:
gpio_defs.h:220
PAD_NF
#define PAD_NF(pin, func, pull)
Definition:
gpio_defs.h:208
PAD_GPI
#define PAD_GPI(pin, pull)
Definition:
gpio_defs.h:216
GPIO_14
#define GPIO_14
Definition:
gpio.h:35
GPIO_13
#define GPIO_13
Definition:
gpio.h:34
NULL
#define NULL
Definition:
stddef.h:19
uint32_t
unsigned int uint32_t
Definition:
stdint.h:14
soc_amd_gpio
Definition:
gpio.h:11
src
mainboard
google
zork
variants
trembyle
gpio.c
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