coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gl9763e.h File Reference
#include <types.h>
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Macros

#define VHS   0x884
 
#define VHS_REV_MASK   (0xF << 16)
 
#define VHS_REV_R   (0x0 << 16)
 
#define VHS_REV_M   (0x1 << 16)
 
#define VHS_REV_W   (0x2 << 16)
 
#define SCR   0x8E0
 
#define SCR_AXI_REQ   BIT(9)
 
#define CFG_REG_2   0x8A4
 
#define CFG_REG_2_L0S   BIT(11)
 
#define CFG_REG_2_L1DLY_MAX   (0x3FF << 19)
 
#define PLL_CTL   0x938
 
#define PLL_CTL_SSC   BIT(19)
 
#define EMMC_CTL   0x960
 
#define SLOW_MODE   BIT(3)
 
#define PLL_CTL_2   0x93C
 
#define PLL_CTL_2_MAX_SSC_MASK   (0xFFFF << 16)
 
#define MAX_SSC_30000PPM   (0xF5C3 << 16)
 
#define HW_VER_2   0x8F8
 
#define HW_VER_MASK   0xFFFF
 
#define REVISION_03   0x0011
 
#define SD_CLKRX_DLY   0x934
 
#define CLK_SRC_MASK   (0x3 << 24)
 
#define AFTER_OUTPUT_BUFF   (0x0 << 24)
 
#define HS400_RX_DELAY_MASK   (0xF << 28)
 
#define HS400_RX_DELAY   (0x5 << 28)
 

Macro Definition Documentation

◆ AFTER_OUTPUT_BUFF

#define AFTER_OUTPUT_BUFF   (0x0 << 24)

Definition at line 35 of file gl9763e.h.

◆ CFG_REG_2

#define CFG_REG_2   0x8A4

Definition at line 15 of file gl9763e.h.

◆ CFG_REG_2_L0S

#define CFG_REG_2_L0S   BIT(11)

Definition at line 16 of file gl9763e.h.

◆ CFG_REG_2_L1DLY_MAX

#define CFG_REG_2_L1DLY_MAX   (0x3FF << 19)

Definition at line 17 of file gl9763e.h.

◆ CLK_SRC_MASK

#define CLK_SRC_MASK   (0x3 << 24)

Definition at line 34 of file gl9763e.h.

◆ EMMC_CTL

#define EMMC_CTL   0x960

Definition at line 22 of file gl9763e.h.

◆ HS400_RX_DELAY

#define HS400_RX_DELAY   (0x5 << 28)

Definition at line 37 of file gl9763e.h.

◆ HS400_RX_DELAY_MASK

#define HS400_RX_DELAY_MASK   (0xF << 28)

Definition at line 36 of file gl9763e.h.

◆ HW_VER_2

#define HW_VER_2   0x8F8

Definition at line 29 of file gl9763e.h.

◆ HW_VER_MASK

#define HW_VER_MASK   0xFFFF

Definition at line 30 of file gl9763e.h.

◆ MAX_SSC_30000PPM

#define MAX_SSC_30000PPM   (0xF5C3 << 16)

Definition at line 27 of file gl9763e.h.

◆ PLL_CTL

#define PLL_CTL   0x938

Definition at line 19 of file gl9763e.h.

◆ PLL_CTL_2

#define PLL_CTL_2   0x93C

Definition at line 25 of file gl9763e.h.

◆ PLL_CTL_2_MAX_SSC_MASK

#define PLL_CTL_2_MAX_SSC_MASK   (0xFFFF << 16)

Definition at line 26 of file gl9763e.h.

◆ PLL_CTL_SSC

#define PLL_CTL_SSC   BIT(19)

Definition at line 20 of file gl9763e.h.

◆ REVISION_03

#define REVISION_03   0x0011

Definition at line 31 of file gl9763e.h.

◆ SCR

#define SCR   0x8E0

Definition at line 12 of file gl9763e.h.

◆ SCR_AXI_REQ

#define SCR_AXI_REQ   BIT(9)

Definition at line 13 of file gl9763e.h.

◆ SD_CLKRX_DLY

#define SD_CLKRX_DLY   0x934

Definition at line 33 of file gl9763e.h.

◆ SLOW_MODE

#define SLOW_MODE   BIT(3)

Definition at line 23 of file gl9763e.h.

◆ VHS

#define VHS   0x884

Definition at line 7 of file gl9763e.h.

◆ VHS_REV_M

#define VHS_REV_M   (0x1 << 16)

Definition at line 10 of file gl9763e.h.

◆ VHS_REV_MASK

#define VHS_REV_MASK   (0xF << 16)

Definition at line 8 of file gl9763e.h.

◆ VHS_REV_R

#define VHS_REV_R   (0x0 << 16)

Definition at line 9 of file gl9763e.h.

◆ VHS_REV_W

#define VHS_REV_W   (0x2 << 16)

Definition at line 11 of file gl9763e.h.