coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
msr.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _DENVERTON_NS_MSR_H_
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#define _DENVERTON_NS_MSR_H_
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#define MSR_CORE_THREAD_COUNT 0x35
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#define MSR_PLATFORM_INFO 0xce
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#define PLATFORM_INFO_SET_TDP (1 << 29)
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#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
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#define MSR_FEATURE_CONFIG 0x13c
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#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL
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#define FEATURE_CONFIG_LOCK (1 << 0)
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#define MSR_POWER_MISC 0x120
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#define ENABLE_IA_UNTRUSTED (1 << 6)
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#define IA32_MCG_CAP 0x179
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#define IA32_MCG_CAP_COUNT_MASK 0xff
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#define IA32_MCG_CAP_CTL_P_BIT 8
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#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT)
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#define IA32_MCG_CTL 0x17b
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#define SMM_MCA_CAP_MSR 0x17d
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#define SMM_CPU_SVRSTR_BIT 57
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#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
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#define MSR_FLEX_RATIO 0x194
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#define FLEX_RATIO_LOCK (1 << 20)
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#define FLEX_RATIO_EN (1 << 16)
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/* IA32_MISC_ENABLE 0x1a0 */
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#define THERMAL_MONITOR_ENABLE_BIT (1 << 3)
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#define MSR_MISC_PWR_MGMT 0x1aa
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#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
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#define MSR_TURBO_RATIO_LIMIT 0x1ad
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#define MSR_TEMPERATURE_TARGET 0x1a2
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#define EMRR_PHYS_BASE_MSR 0x1f4
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#define MSR_PRMRR_PHYS_MASK 0x1f5
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#define MSR_POWER_CTL 0x1fc
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#define MSR_LT_LOCK_MEMORY 0x2e7
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#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
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#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
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#define SMM_FEATURE_CONTROL_MSR 0x4e0
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#define SMM_CPU_SAVE_EN (1 << 1)
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#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a
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#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b
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#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c
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#define MSR_C_STATE_LATENCY_CONTROL_3 0x633
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#define MSR_C_STATE_LATENCY_CONTROL_4 0x634
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#define MSR_C_STATE_LATENCY_CONTROL_5 0x635
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#define IRTL_VALID (1 << 15)
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#define IRTL_1_NS (0 << 10)
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#define IRTL_32_NS (1 << 10)
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#define IRTL_1024_NS (2 << 10)
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#define IRTL_32768_NS (3 << 10)
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#define IRTL_1048576_NS (4 << 10)
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#define IRTL_33554432_NS (5 << 10)
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#define IRTL_RESPONSE_MASK (0x3ff)
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#define MSR_COUNTER_24_MHZ 0x637
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/* long duration in low dword, short duration in high dword */
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#define MSR_PKG_POWER_LIMIT 0x610
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#define PKG_POWER_LIMIT_MASK 0x7fff
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#define PKG_POWER_LIMIT_EN (1 << 15)
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#define PKG_POWER_LIMIT_CLAMP (1 << 16)
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#define PKG_POWER_LIMIT_TIME_SHIFT 17
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#define PKG_POWER_LIMIT_TIME_MASK 0x7f
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#define MSR_VR_CURRENT_CONFIG 0x601
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#define MSR_VR_MISC_CONFIG 0x603
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#define MSR_PKG_POWER_SKU_UNIT 0x606
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#define MSR_PKG_POWER_SKU 0x614
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#define MSR_DDR_RAPL_LIMIT 0x618
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#define MSR_VR_MISC_CONFIG2 0x636
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#define MSR_PP0_POWER_LIMIT 0x638
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#define MSR_PP1_POWER_LIMIT 0x640
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#define MSR_CONFIG_TDP_NOMINAL 0x648
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#define MSR_CONFIG_TDP_LEVEL1 0x649
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#define MSR_CONFIG_TDP_LEVEL2 0x64a
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#define MSR_CONFIG_TDP_CONTROL 0x64b
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#define MSR_TURBO_ACTIVATION_RATIO 0x64c
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/* SMM save state MSRs */
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#define SMBASE_MSR 0xc20
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#define IEDBASE_MSR 0xc22
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/* MTRRcap_MSR bits */
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#define SMRR_SUPPORTED (1 << 11)
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#define PRMRR_SUPPORTED (1 << 12)
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/* Read BCLK from MSR */
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unsigned
int
bus_freq_khz
(
void
);
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#endif
/* _DENVERTON_NS_MSR_H_ */
bus_freq_khz
unsigned int bus_freq_khz(void)
Definition:
tsc_freq.c:7
src
soc
intel
denverton_ns
include
soc
msr.h
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