3 #ifndef SOC_MEDIATEK_MT8183_MCUCFG_H
4 #define SOC_MEDIATEK_MT8183_MCUCFG_H
6 #include <soc/addressmap.h>
check_member(mt8173_mcucfg_regs, mcusys_rw_rsvd1, 0x688)
static struct mt8183_mcucfg_regs *const mt8183_mcucfg
u32 psys_hang_monitor_ctrl0
u32 mp0_cpu1_avg_stall_ratio_ctrl
u32 mp_gen_timer_reset_mask_6
u32 gpu_hang_monitor_ctrl1
u32 dfd_internal_counter_return
u32 cpusys0_cpu2_spmc_ctl
u32 mp_gen_timer_reset_mask_1
u32 mp0_cpu_avg_stall_ratio
u32 dfd_internal_chain_length_2
u32 dfd_internal_mcsib_sel_status
u32 cci_bw_pmu_cnt0to3_mask
u32 mp0_cache_mem_delsel0
u32 cci_bw_pmu_cnt0to1_sel
u32 mp0_cpu3_non_wfi_counter
u32 dfd_internal_shift_clk_ratio
u32 gpu_hang_monitor_ctrl0
u32 cci_bw_pmu_id_ext_cnt4to7
u32 mp0_ca7l_dbg_pwr_ctrl
u32 mp0_cpu1_non_wfi_counter
u32 mp0_l2_cache_parity1_rdata
u32 mp0_hang_monitor_ctrl1
u32 mp0_cpu3_stall_counter
u32 mp0_sync_dcm_cgavg_rfact
u32 mp0_sync_dcm_cgavg_fact
u32 mp0_ca7l_cache_config
u32 dfd_internal_sram_delsel
u32 mp1_sw_rst_wait_cycle
u32 mp0_cpu0_non_wfi_counter
u32 mp0_cpu1_stall_counter
u32 mp0_cpu2_stall_counter
u32 cci_bw_pmu_cnt2to3_sel
u32 dfd_internal_chain_legth_0
u32 cpusys0_cpu3_spmc_ctl
u32 mp_sync_dcm_cluster_config
u32 mp_gen_timer_reset_mask_2
u32 cci_bw_pmu_id_ext_cnt0to3
u32 cpusys0_spark_debug_overwrite
u32 mp0_sync_dcm_cgavg_ctrl
u32 mp0_cpu0_stall_counter
u32 mp0_hang_monitor_ctrl0
u32 cci_bw_pmu_cnt6to7_sel
u32 dfd_internal_chain_length_1
u32 cci_bw_pmu_mask_ext_cnt4to7
u32 dfd_internal_sram_base_addr
u32 mp_gen_timer_reset_mask_secur_en
u32 mp0_cpu3_avg_stall_ratio_ctrl
u32 cci_bw_pmu_cnt4to5_sel
u32 mp1_hang_monitor_ctrl1
u32 mp0_cpu2_non_wfi_counter
u32 dfd_internal_test_so_1
u32 misccfg_sec_vio_status1
u32 mp0_cache_mem_delsel1
u32 mp1_hang_monitor_ctrl0
u32 mbista_mcsib_sf1_result
u32 mp_cci_adb400_dcm_config
u32 dfd_internal_chain_length_3
u32 cpusys0_cpu0_spmc_ctl
u32 mcusys_bus_fabric_dcm_ctrl
u32 mp0_cpu0_avg_stall_ratio_ctrl
u32 misccfg_sec_vio_status0
u32 dfd_internal_test_so_over_64
u32 mp0_ca53_specific_ctrl
u32 mp2_hang_monitor_ctrl0
u32 mp_gen_timer_reset_mask_3
u32 cci_bw_pmu_cnt4to7_mask
u32 mp_gen_timer_reset_mask_4
u32 cpusys0_cpu1_spmc_ctl
u32 mbista_mcsib_sf2_result
u32 dfd_internal_test_so_0
u32 psys_hang_monitor_ctrl1
u32 mp_gen_timer_reset_mask_5
u32 dfd_internal_mask_out
u32 mp0_l2_cache_parity2_rdata
u32 mcusys_gic_peribase_a
u32 mp0_avg_stall_ratio_status
u32 hack_ice_rom_table_access
u32 mp_gen_timer_reset_mask_7
u32 mp_gen_timer_reset_mask_0
u32 mp0_cpu2_avg_stall_ratio_ctrl
u32 dfd_internal_sw_ns_trigger
u32 cci_bw_pmu_mask_ext_cnt0to3
u32 cpusys0_sparkvretcntrl
u32 dfd_internal_sram_access
u32 mp2_hang_monitor_ctrl1
u32 dfd_internal_num_of_test_so_gp