coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Macros | Functions
usb.c File Reference
#include <device/mmio.h>
#include <console/console.h>
#include <delay.h>
#include <soc/clock.h>
#include <soc/iomap.h>
#include <soc/usb.h>
Include dependency graph for usb.c:

Go to the source code of this file.

Macros

#define PHY_CTRL0_ADDR   0x000
 USB Hardware registers. More...
 
#define PHY_CTRL1_ADDR   0x004
 
#define PHY_CTRL2_ADDR   0x008
 
#define PHY_CTRL3_ADDR   0x00C
 
#define PHY_CTRL4_ADDR   0x010
 
#define PHY_MISC_ADDR   0x024
 
#define PHY_IPG_ADDR   0x030
 
#define PHY_CTRL0_VAL   0xA4600015
 
#define PHY_CTRL1_VAL   0x09500000
 
#define PHY_CTRL2_VAL   0x00058180
 
#define PHY_CTRL3_VAL   0x6DB6DCD6
 
#define PHY_CTRL4_VAL   0x836DB6DB
 
#define PHY_MISC_VAL   0x3803FB0C
 
#define PHY_IPG_VAL   0x47323232
 
#define USB_HOST3_PHY_BASE   ((void *)0x8a00000)
 
#define USB_HOST3_BALDUR_PHY_BASE   ((void *)0xa6000)
 
#define GCC_USB3_RST_CTRL   ((void *)0x0181E038)
 
#define DWC3_GCTL   0xc110
 
#define DWC3_GUSB3PIPECTL(n)   (0xc2c0 + (n * 0x04))
 
#define DWC3_GUSB2PHYCFG(n)   (0xc200 + (n * 0x04))
 
#define DWC3_GUSB3PIPECTL_PHYSOFTRST   (1 << 31)
 
#define DWC3_GUSB3PIPECTL_SUSPHY   (1 << 17)
 
#define DWC3_GCTL_CORESOFTRESET   (1 << 11)
 
#define DWC3_GCTL_PRTCAPDIR(n)   ((n) << 12)
 
#define DWC3_GCTL_PRTCAP_OTG   3
 
#define DWC3_DCTL_CSFTRST   (1 << 30)
 
#define DWC3_GSNPSID   0xc120
 
#define DWC3_DCTL   0xc704
 
#define DWC3_GUSB2PHYCFG_PHYSOFTRST   (1 << 31)
 
#define DWC3_GUSB2PHYCFG_SUSPHY   (1 << 6)
 
#define DWC3_GSNPSID_MASK   0xffff0000
 
#define DWC3_GEVTEN   0xc114
 
#define DWC3_GCTL_SCALEDOWN(n)   ((n) << 4)
 
#define DWC3_GCTL_SCALEDOWN_MASK   DWC3_GCTL_SCALEDOWN(3)
 
#define DWC3_GCTL_DISSCRAMBLE   (1 << 3)
 
#define DWC3_GCTL_DSBLCLKGTNG   (1 << 0)
 
#define DWC3_GCTL_U2RSTECN   (1 << 16)
 
#define DWC3_REVISION_190A   0x5533190a
 
#define USB30_HS_PHY_CTRL   0x00000010
 
#define SW_SESSVLD   (0x01 << 0x1C)
 
#define UTMI_OTG_VBUS_VALID   (0x01 << 0x14)
 
#define USB30_SS_PHY_CTRL   0x00000030
 
#define LANE0_PWR_PRESENT   (0x01 << 0x18)
 

Functions

static void setup_dwc3 (void)
 
static void qscratch_write (void *base, u32 offset, u32 val)
 Write register. More...
 
static void qscratch_write_readback (void *base, u32 offset, const u32 mask, u32 val)
 Write register and read back masked value to confirm it is written. More...
 
static void dwc3_ipq40xx_enable_vbus_valid (void)
 
static void qcom_baldur_hs_phy_init (void)
 
static void qcom_uni_ss_phy_init (void)
 
void setup_usb_host1 (void)
 

Macro Definition Documentation

◆ DWC3_DCTL

#define DWC3_DCTL   0xc704

Definition at line 45 of file usb.c.

◆ DWC3_DCTL_CSFTRST

#define DWC3_DCTL_CSFTRST   (1 << 30)

Definition at line 43 of file usb.c.

◆ DWC3_GCTL

#define DWC3_GCTL   0xc110

Definition at line 33 of file usb.c.

◆ DWC3_GCTL_CORESOFTRESET

#define DWC3_GCTL_CORESOFTRESET   (1 << 11)

Definition at line 40 of file usb.c.

◆ DWC3_GCTL_DISSCRAMBLE

#define DWC3_GCTL_DISSCRAMBLE   (1 << 3)

Definition at line 55 of file usb.c.

◆ DWC3_GCTL_DSBLCLKGTNG

#define DWC3_GCTL_DSBLCLKGTNG   (1 << 0)

Definition at line 56 of file usb.c.

◆ DWC3_GCTL_PRTCAP_OTG

#define DWC3_GCTL_PRTCAP_OTG   3

Definition at line 42 of file usb.c.

◆ DWC3_GCTL_PRTCAPDIR

#define DWC3_GCTL_PRTCAPDIR (   n)    ((n) << 12)

Definition at line 41 of file usb.c.

◆ DWC3_GCTL_SCALEDOWN

#define DWC3_GCTL_SCALEDOWN (   n)    ((n) << 4)

Definition at line 53 of file usb.c.

◆ DWC3_GCTL_SCALEDOWN_MASK

#define DWC3_GCTL_SCALEDOWN_MASK   DWC3_GCTL_SCALEDOWN(3)

Definition at line 54 of file usb.c.

◆ DWC3_GCTL_U2RSTECN

#define DWC3_GCTL_U2RSTECN   (1 << 16)

Definition at line 57 of file usb.c.

◆ DWC3_GEVTEN

#define DWC3_GEVTEN   0xc114

Definition at line 51 of file usb.c.

◆ DWC3_GSNPSID

#define DWC3_GSNPSID   0xc120

Definition at line 44 of file usb.c.

◆ DWC3_GSNPSID_MASK

#define DWC3_GSNPSID_MASK   0xffff0000

Definition at line 50 of file usb.c.

◆ DWC3_GUSB2PHYCFG

#define DWC3_GUSB2PHYCFG (   n)    (0xc200 + (n * 0x04))

Definition at line 35 of file usb.c.

◆ DWC3_GUSB2PHYCFG_PHYSOFTRST

#define DWC3_GUSB2PHYCFG_PHYSOFTRST   (1 << 31)

Definition at line 48 of file usb.c.

◆ DWC3_GUSB2PHYCFG_SUSPHY

#define DWC3_GUSB2PHYCFG_SUSPHY   (1 << 6)

Definition at line 49 of file usb.c.

◆ DWC3_GUSB3PIPECTL

#define DWC3_GUSB3PIPECTL (   n)    (0xc2c0 + (n * 0x04))

Definition at line 34 of file usb.c.

◆ DWC3_GUSB3PIPECTL_PHYSOFTRST

#define DWC3_GUSB3PIPECTL_PHYSOFTRST   (1 << 31)

Definition at line 38 of file usb.c.

◆ DWC3_GUSB3PIPECTL_SUSPHY

#define DWC3_GUSB3PIPECTL_SUSPHY   (1 << 17)

Definition at line 39 of file usb.c.

◆ DWC3_REVISION_190A

#define DWC3_REVISION_190A   0x5533190a

Definition at line 58 of file usb.c.

◆ GCC_USB3_RST_CTRL

#define GCC_USB3_RST_CTRL   ((void *)0x0181E038)

Definition at line 31 of file usb.c.

◆ LANE0_PWR_PRESENT

#define LANE0_PWR_PRESENT   (0x01 << 0x18)

Definition at line 65 of file usb.c.

◆ PHY_CTRL0_ADDR

#define PHY_CTRL0_ADDR   0x000

USB Hardware registers.

Definition at line 13 of file usb.c.

◆ PHY_CTRL0_VAL

#define PHY_CTRL0_VAL   0xA4600015

Definition at line 21 of file usb.c.

◆ PHY_CTRL1_ADDR

#define PHY_CTRL1_ADDR   0x004

Definition at line 14 of file usb.c.

◆ PHY_CTRL1_VAL

#define PHY_CTRL1_VAL   0x09500000

Definition at line 22 of file usb.c.

◆ PHY_CTRL2_ADDR

#define PHY_CTRL2_ADDR   0x008

Definition at line 15 of file usb.c.

◆ PHY_CTRL2_VAL

#define PHY_CTRL2_VAL   0x00058180

Definition at line 23 of file usb.c.

◆ PHY_CTRL3_ADDR

#define PHY_CTRL3_ADDR   0x00C

Definition at line 16 of file usb.c.

◆ PHY_CTRL3_VAL

#define PHY_CTRL3_VAL   0x6DB6DCD6

Definition at line 24 of file usb.c.

◆ PHY_CTRL4_ADDR

#define PHY_CTRL4_ADDR   0x010

Definition at line 17 of file usb.c.

◆ PHY_CTRL4_VAL

#define PHY_CTRL4_VAL   0x836DB6DB

Definition at line 25 of file usb.c.

◆ PHY_IPG_ADDR

#define PHY_IPG_ADDR   0x030

Definition at line 19 of file usb.c.

◆ PHY_IPG_VAL

#define PHY_IPG_VAL   0x47323232

Definition at line 27 of file usb.c.

◆ PHY_MISC_ADDR

#define PHY_MISC_ADDR   0x024

Definition at line 18 of file usb.c.

◆ PHY_MISC_VAL

#define PHY_MISC_VAL   0x3803FB0C

Definition at line 26 of file usb.c.

◆ SW_SESSVLD

#define SW_SESSVLD   (0x01 << 0x1C)

Definition at line 61 of file usb.c.

◆ USB30_HS_PHY_CTRL

#define USB30_HS_PHY_CTRL   0x00000010

Definition at line 60 of file usb.c.

◆ USB30_SS_PHY_CTRL

#define USB30_SS_PHY_CTRL   0x00000030

Definition at line 64 of file usb.c.

◆ USB_HOST3_BALDUR_PHY_BASE

#define USB_HOST3_BALDUR_PHY_BASE   ((void *)0xa6000)

Definition at line 30 of file usb.c.

◆ USB_HOST3_PHY_BASE

#define USB_HOST3_PHY_BASE   ((void *)0x8a00000)

Definition at line 29 of file usb.c.

◆ UTMI_OTG_VBUS_VALID

#define UTMI_OTG_VBUS_VALID   (0x01 << 0x14)

Definition at line 62 of file usb.c.

Function Documentation

◆ dwc3_ipq40xx_enable_vbus_valid()

static void dwc3_ipq40xx_enable_vbus_valid ( void  )
static

Definition at line 109 of file usb.c.

References LANE0_PWR_PRESENT, qscratch_write_readback(), SW_SESSVLD, USB30_HS_PHY_CTRL, USB30_SS_PHY_CTRL, and UTMI_OTG_VBUS_VALID.

Referenced by setup_usb_host1().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ qcom_baldur_hs_phy_init()

static void qcom_baldur_hs_phy_init ( void  )
static

Definition at line 122 of file usb.c.

References GCC_USB3_RST_CTRL, mdelay(), PHY_CTRL0_ADDR, PHY_CTRL0_VAL, PHY_CTRL1_ADDR, PHY_CTRL1_VAL, PHY_CTRL2_ADDR, PHY_CTRL2_VAL, PHY_CTRL3_ADDR, PHY_CTRL3_VAL, PHY_CTRL4_ADDR, PHY_CTRL4_VAL, PHY_IPG_ADDR, PHY_IPG_VAL, PHY_MISC_ADDR, PHY_MISC_VAL, read32(), USB_HOST3_BALDUR_PHY_BASE, and write32().

Referenced by setup_dwc3().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ qcom_uni_ss_phy_init()

static void qcom_uni_ss_phy_init ( void  )
static

Definition at line 162 of file usb.c.

References GCC_USB3_RST_CTRL, mdelay(), read32(), and write32().

Referenced by setup_dwc3().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ qscratch_write()

static void qscratch_write ( void *  base,
u32  offset,
u32  val 
)
inlinestatic

Write register.

Parameters
base- PHY base virtual address.
offset- register offset.
val- value to write.

Definition at line 76 of file usb.c.

References base, offset, val, and write32().

Here is the call graph for this function:

◆ qscratch_write_readback()

static void qscratch_write_readback ( void *  base,
u32  offset,
const u32  mask,
u32  val 
)
inlinestatic

Write register and read back masked value to confirm it is written.

Parameters
base- base virtual address.
offset- register offset.
mask- register bitmask specifying what should be updated
val- value to write.

Definition at line 89 of file usb.c.

References base, BIOS_INFO, mask, offset, printk, read32(), val, and write32().

Referenced by dwc3_ipq40xx_enable_vbus_valid().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ setup_dwc3()

void setup_dwc3 ( void  )
static

Definition at line 179 of file usb.c.

References BIOS_INFO, DWC3_DCTL, DWC3_DCTL_CSFTRST, DWC3_GCTL, DWC3_GCTL_CORESOFTRESET, DWC3_GCTL_DISSCRAMBLE, DWC3_GCTL_DSBLCLKGTNG, DWC3_GCTL_PRTCAP_OTG, DWC3_GCTL_PRTCAPDIR, DWC3_GCTL_SCALEDOWN_MASK, DWC3_GCTL_U2RSTECN, DWC3_GSNPSID, DWC3_GSNPSID_MASK, DWC3_GUSB2PHYCFG, DWC3_GUSB2PHYCFG_PHYSOFTRST, DWC3_GUSB2PHYCFG_SUSPHY, DWC3_GUSB3PIPECTL, DWC3_GUSB3PIPECTL_PHYSOFTRST, DWC3_GUSB3PIPECTL_SUSPHY, DWC3_REVISION_190A, mdelay(), printk, qcom_baldur_hs_phy_init(), qcom_uni_ss_phy_init(), read32(), udelay(), USB_HOST3_PHY_BASE, and write32().

Referenced by setup_usb_host1().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ setup_usb_host1()

void setup_usb_host1 ( void  )

Definition at line 274 of file usb.c.