3 #ifndef __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__
4 #define __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__
14 #include <soc/dramc_soc.h>
16 #define DRAMC_PARAM_HEADER_VERSION 1
int initialize_dramc_param(void *blob, u16 config)
struct dramc_param * get_dramc_param_from_blob(void *blob)
const struct sdram_info * get_sdram_config(void)
void dump_param_header(const void *blob)
#define DQ_DATA_WIDTH_LP4
struct ddr_base_info ddr_info
struct sdram_params freq_params[DRAM_DFS_SHU_MAX]
struct dramc_param_header header
struct dramc_data dramc_datas
void(* do_putc)(unsigned char c)
Defines the SDRAM parameter structure.
u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]
u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]
u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]
u8 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]
u8 gating_MCK[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]
s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4]
u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]
u8 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]
u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]
u8 cbt_ca_prebit_dly[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER]
u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]
u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]
u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]
u8 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]
s8 duty_clk_delay[CHANNEL_MAX]
s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4]
u8 rx_datlat[CHANNEL_MAX][RANK_MAX]
u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX]
u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]
u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]
u8 rx_best_vref[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]
u8 tx_window_vref[CHANNEL_MAX][RANK_MAX]
s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER]
u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]
u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]
#define c(value, pmcreg, dst_bits)
typedef void(X86APIP X86EMU_intrFuncs)(int num)