coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
mtcmos.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/mmio.h>
4 #include <soc/infracfg.h>
5 #include <soc/mtcmos.h>
6 
7 enum {
8  DISP_PROT_STEP1_0_MASK = 0x05015405,
9  DISP_PROT_STEP1_1_MASK = 0x00001100,
10  DISP_PROT_STEP2_0_MASK = 0x00800040,
11  DISP_PROT_STEP2_1_MASK = 0x0a02800a,
12  DISP_PROT_STEP2_2_MASK = 0x00002200,
13 
15 };
16 
18 {
29 }
30 
32 {
35 }
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
@ DISP_PROT_STEP2_1_MASK
Definition: mtcmos.c:11
@ DISP_PROT_STEP1_0_MASK
Definition: mtcmos.c:9
@ DISP_PROT_STEP2_0_MASK
Definition: mtcmos.c:10
void mtcmos_protect_display_bus(void)
Definition: mtcmos.c:14
void mtcmos_protect_audio_bus(void)
Definition: mtcmos.c:20
static struct mt8192_infracfg_regs *const mt8192_infracfg
Definition: infracfg.h:416
@ DISP_PROT_STEP1_1_MASK
Definition: mtcmos.c:9
@ AUDIO_PROT_STEP1_0_MASK
Definition: mtcmos.c:14
@ DISP_PROT_STEP2_2_MASK
Definition: mtcmos.c:12
u32 infra_topaxi_protecten_mm_clr_2
Definition: infracfg.h:333
u32 infra_topaxi_protecten_clr
Definition: infracfg.h:101
u32 infra_topaxi_protecten_mm_clr
Definition: infracfg.h:114
u32 infra_topaxi_protecten_clr_2
Definition: infracfg.h:190