1 #ifndef CPU_PPC64_SPR_H
2 #define CPU_PPC64_SPR_H
4 #include <arch/byteorder.h>
9 #define SPR_PVR_REV_MASK (PPC_BITMASK(52, 55) | PPC_BITMASK(60, 63))
10 #define SPR_PVR_REV(maj, min) (PPC_SHIFT((maj), 55) | PPC_SHIFT((min), 63))
12 #define SPR_HSPRG0 0x130
13 #define SPR_HSPRG1 0x131
15 #define SPR_HRMOR 0x139
17 #define SPR_HMER 0x150
19 #define SPR_HMER_MALFUNCTION_ALERT PPC_BIT(0)
20 #define SPR_HMER_PROC_RECV_DONE PPC_BIT(2)
21 #define SPR_HMER_PROC_RECV_ERROR_MASKED PPC_BIT(3)
22 #define SPR_HMER_TFAC_ERROR PPC_BIT(4)
23 #define SPR_HMER_TFMR_PARITY_ERROR PPC_BIT(5)
24 #define SPR_HMER_XSCOM_FAIL PPC_BIT(8)
25 #define SPR_HMER_XSCOM_DONE PPC_BIT(9)
26 #define SPR_HMER_PROC_RECV_AGAIN PPC_BIT(11)
27 #define SPR_HMER_WARN_RISE PPC_BIT(14)
28 #define SPR_HMER_WARN_FALL PPC_BIT(15)
29 #define SPR_HMER_SCOM_FIR_HMI PPC_BIT(16)
30 #define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17)
31 #define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20)
32 #define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21, 23)
33 #define SPR_HMER_XSCOM_OCCUPIED PPC_BIT(23)
41 asm volatile(
"mfspr %0,%1" :
"=r"(
val) :
"i"(spr) :
"memory");
47 asm volatile(
"mtspr %0, %1" ::
"i"(spr),
"r"(
val) :
"memory");
63 asm volatile(
"mfmsr %0" :
"=r"(
val) ::
"memory");
static uint64_t pvr_revision(void)
static void write_spr(int spr, uint64_t val)
static uint64_t read_hmer(void)
static uint64_t read_spr(int spr)
static void clear_hmer(void)
static uint64_t read_msr(void)
unsigned long long uint64_t