4 #include <soc/romstage.h>
10 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f,
11 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03,
12 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e,
13 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15
16 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02,
17 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f,
18 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17,
19 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f
22 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a,
23 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04,
24 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d,
25 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11
28 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07,
29 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d,
30 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12,
31 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f
40 memupd->FspmConfig.Package = 0x1;
41 memupd->FspmConfig.Profile = 0xB;
42 memupd->FspmConfig.MemoryDown = 0x1;
43 memupd->FspmConfig.DDR3LPageSize = 0x0;
44 memupd->FspmConfig.DDR3LASR = 0x0;
45 memupd->FspmConfig.ScramblerSupport = 0x1;
46 memupd->FspmConfig.ChannelHashMask = 0x36;
47 memupd->FspmConfig.SliceHashMask = 0x9;
48 memupd->FspmConfig.InterleavedMode = 0x2;
49 memupd->FspmConfig.ChannelsSlicesEnable = 0x0;
50 memupd->FspmConfig.MinRefRate2xEnable = 0x0;
51 memupd->FspmConfig.DualRankSupportEnable = 0x1;
52 memupd->FspmConfig.RmtMode = 0x0;
53 memupd->FspmConfig.MemorySizeLimit = 0x1800;
54 memupd->FspmConfig.LowMemoryMaxValue = 0x0;
55 memupd->FspmConfig.DisableFastBoot = 0x0;
56 memupd->FspmConfig.HighMemoryMaxValue = 0x0;
57 memupd->FspmConfig.DIMM0SPDAddress = 0x0;
58 memupd->FspmConfig.DIMM1SPDAddress = 0x0;
59 memupd->FspmConfig.Ch0_RankEnable = 0x3;
60 memupd->FspmConfig.Ch0_DeviceWidth = 0x1;
61 memupd->FspmConfig.Ch0_DramDensity = 0x2;
62 memupd->FspmConfig.Ch0_Option = 0x3;
63 memupd->FspmConfig.Ch0_OdtConfig = 0x0;
64 memupd->FspmConfig.Ch0_TristateClk1 = 0x0;
65 memupd->FspmConfig.Ch0_Mode2N = 0x0;
66 memupd->FspmConfig.Ch0_OdtLevels = 0x0;
67 memupd->FspmConfig.Ch1_RankEnable = 0x3;
68 memupd->FspmConfig.Ch1_DeviceWidth = 0x1;
69 memupd->FspmConfig.Ch1_DramDensity = 0x2;
70 memupd->FspmConfig.Ch1_Option = 0x3;
71 memupd->FspmConfig.Ch1_OdtConfig = 0x0;
72 memupd->FspmConfig.Ch1_TristateClk1 = 0x0;
73 memupd->FspmConfig.Ch1_Mode2N = 0x0;
74 memupd->FspmConfig.Ch1_OdtLevels = 0x0;
75 memupd->FspmConfig.Ch2_RankEnable = 0x3;
76 memupd->FspmConfig.Ch2_DeviceWidth = 0x1;
77 memupd->FspmConfig.Ch2_DramDensity = 0x2;
78 memupd->FspmConfig.Ch2_Option = 0x3;
79 memupd->FspmConfig.Ch2_OdtConfig = 0x0;
80 memupd->FspmConfig.Ch2_TristateClk1 = 0x0;
81 memupd->FspmConfig.Ch2_Mode2N = 0x0;
82 memupd->FspmConfig.Ch2_OdtLevels = 0x0;
83 memupd->FspmConfig.Ch3_RankEnable = 0x3;
84 memupd->FspmConfig.Ch3_DeviceWidth = 0x1;
85 memupd->FspmConfig.Ch3_DramDensity = 0x2;
86 memupd->FspmConfig.Ch3_Option = 0x3;
87 memupd->FspmConfig.Ch3_OdtConfig = 0x0;
88 memupd->FspmConfig.Ch3_TristateClk1 = 0x0;
89 memupd->FspmConfig.Ch3_Mode2N = 0x0;
90 memupd->FspmConfig.Ch3_OdtLevels = 0x0;
91 memupd->FspmConfig.RmtCheckRun = 0x0;
92 memupd->FspmConfig.MrcDataSaving = 0x0;
93 memupd->FspmConfig.MrcFastBoot = 0x0;
104 memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0;
105 memupd->FspmConfig.MsgLevelMask = 0x0;
void * memcpy(void *dest, const void *src, size_t n)
static const struct pad_config gpio_table[]
void mainboard_memory_init_params(FSPM_UPD *mupd)
static const uint8_t Ch3_Bit_swizzling[]
static const uint8_t Ch0_Bit_swizzling[]
static const uint8_t Ch2_Bit_swizzling[]
static const uint8_t Ch1_Bit_swizzling[]
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO