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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <stdint.h>
Go to the source code of this file.
Macros | |
#define | ABORT_BASE_ADDRESS 0xfeb00000 |
#define | ABORT_BASE_SIZE 0x00100000 |
#define | PMC_BASE_ADDRESS 0xfed03000 |
#define | PMC_BASE_SIZE 0x400 |
#define | IO_BASE_ADDRESS 0xfed0c000 |
#define | IO_BASE_OFFSET_GPSCORE 0x0000 |
#define | IO_BASE_OFFSET_GPNCORE 0x1000 |
#define | IO_BASE_OFFSET_GPSSUS 0x2000 |
#define | IO_BASE_SIZE 0x4000 |
#define | ILB_BASE_ADDRESS 0xfed08000 |
#define | ILB_BASE_SIZE 0x400 |
#define | SPI_BASE_ADDRESS 0xfed01000 |
#define | SPI_BASE_SIZE 0x400 |
#define | MPHY_BASE_ADDRESS 0xfef00000 |
#define | MPHY_BASE_SIZE 0x100000 |
#define | PUNIT_BASE_ADDRESS 0xfed05000 |
#define | PUNIT_BASE_SIZE 0x800 |
#define | RCBA_BASE_ADDRESS 0xfed1c000 |
#define | RCBA_BASE_SIZE 0x400 |
#define | TEMP_BASE_ADDRESS 0xfd000000 |
#define | ACPI_BASE_ADDRESS 0x0400 |
#define | ACPI_BASE_SIZE 0x80 |
#define | GPIO_BASE_ADDRESS 0x0500 |
#define | GPIO_BASE_SIZE 0x100 |
#define | SMBUS_BASE_ADDRESS 0xefa0 |
Functions | |
uint32_t | nc_read_top_of_low_memory (void) |
Definition at line 52 of file northcluster.c.
References BUNIT_BMBOUND, and iosf_bunit_read().