coreboot
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addressmap.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_
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#define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_
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#define AOSS_CC_BASE 0x0C2A0000
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#define GCC_BASE 0x00100000
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#define QSPI_BASE 0x088DC000
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#define TLMM_NORTH_TILE_BASE 0x03900000
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#define TLMM_SOUTH_TILE_BASE 0x03D00000
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#define TLMM_WEST_TILE_BASE 0x03500000
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#define SILVER_PLL_BASE 0x18280000
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#define L3_PLL_BASE 0x18284000
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#define DISP_CC_BASE 0x0AF00000
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/*
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* QUP SERIAL ENGINE BASE ADDRESSES
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*/
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/* QUPV3_0 */
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#define QUP_SERIAL0_BASE 0x00880000
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#define QUP_SERIAL1_BASE 0x00884000
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#define QUP_SERIAL2_BASE 0x00888000
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#define QUP_SERIAL3_BASE 0x0088C000
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#define QUP_SERIAL4_BASE 0x00890000
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#define QUP_SERIAL5_BASE 0x00894000
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#define QUP_WRAP0_BASE 0x008C0000
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/* QUPV3_1 */
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#define QUP_SERIAL6_BASE 0x00A80000
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#define QUP_SERIAL7_BASE 0x00A84000
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#define QUP_SERIAL8_BASE 0x00A88000
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#define QUP_SERIAL9_BASE 0x00A8C000
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#define QUP_SERIAL10_BASE 0x00A90000
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#define QUP_SERIAL11_BASE 0x00A94000
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#define QUP_WRAP1_BASE 0x00AC0000
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/*
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* USB BASE ADDRESSES
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*/
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#define QFPROM_BASE 0x00780000
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#define QUSB_PRIM_PHY_BASE 0x088e3000
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#define QUSB_PRIM_PHY_DIG_BASE 0x088e3200
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#define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000
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#define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200
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#define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400
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#define QMP_PHY_PCS_REG_BASE 0x088e9c00
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#define USB_HOST_DWC3_BASE 0x0a60c100
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/* SC7180 QSPI GPIO PINS */
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#define QSPI_CLK GPIO(63)
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#define QSPI_DATA_0 GPIO(64)
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#define QSPI_DATA_1 GPIO(65)
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#define QSPI_CS GPIO(68)
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#define GPIO_FUNC_QSPI_DATA_0 GPIO64_FUNC_QSPI_DATA_0
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#define GPIO_FUNC_QSPI_DATA_1 GPIO65_FUNC_QSPI_DATA_1
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#define GPIO_FUNC_QSPI_CLK GPIO63_FUNC_QSPI_CLK
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/* SDHC TLMM Registers */
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#define SDC1_TLMM_CFG_ADDR 0x03D7A000
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#define SDC2_TLMM_CFG_ADDR 0x03D7B000
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#endif
/* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */
src
soc
qualcomm
sc7180
include
soc
addressmap.h
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