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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
| #define | AOSS_CC_BASE 0x0C2A0000 |
| #define | GCC_BASE 0x00100000 |
| #define | QSPI_BASE 0x088DC000 |
| #define | TLMM_NORTH_TILE_BASE 0x03900000 |
| #define | TLMM_SOUTH_TILE_BASE 0x03D00000 |
| #define | TLMM_WEST_TILE_BASE 0x03500000 |
| #define | SILVER_PLL_BASE 0x18280000 |
| #define | L3_PLL_BASE 0x18284000 |
| #define | DISP_CC_BASE 0x0AF00000 |
| #define | QUP_SERIAL0_BASE 0x00880000 |
| #define | QUP_SERIAL1_BASE 0x00884000 |
| #define | QUP_SERIAL2_BASE 0x00888000 |
| #define | QUP_SERIAL3_BASE 0x0088C000 |
| #define | QUP_SERIAL4_BASE 0x00890000 |
| #define | QUP_SERIAL5_BASE 0x00894000 |
| #define | QUP_WRAP0_BASE 0x008C0000 |
| #define | QUP_SERIAL6_BASE 0x00A80000 |
| #define | QUP_SERIAL7_BASE 0x00A84000 |
| #define | QUP_SERIAL8_BASE 0x00A88000 |
| #define | QUP_SERIAL9_BASE 0x00A8C000 |
| #define | QUP_SERIAL10_BASE 0x00A90000 |
| #define | QUP_SERIAL11_BASE 0x00A94000 |
| #define | QUP_WRAP1_BASE 0x00AC0000 |
| #define | QFPROM_BASE 0x00780000 |
| #define | QUSB_PRIM_PHY_BASE 0x088e3000 |
| #define | QUSB_PRIM_PHY_DIG_BASE 0x088e3200 |
| #define | QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 |
| #define | QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 |
| #define | QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 |
| #define | QMP_PHY_PCS_REG_BASE 0x088e9c00 |
| #define | USB_HOST_DWC3_BASE 0x0a60c100 |
| #define | QSPI_CLK GPIO(63) |
| #define | QSPI_DATA_0 GPIO(64) |
| #define | QSPI_DATA_1 GPIO(65) |
| #define | QSPI_CS GPIO(68) |
| #define | GPIO_FUNC_QSPI_DATA_0 GPIO64_FUNC_QSPI_DATA_0 |
| #define | GPIO_FUNC_QSPI_DATA_1 GPIO65_FUNC_QSPI_DATA_1 |
| #define | GPIO_FUNC_QSPI_CLK GPIO63_FUNC_QSPI_CLK |
| #define | SDC1_TLMM_CFG_ADDR 0x03D7A000 |
| #define | SDC2_TLMM_CFG_ADDR 0x03D7B000 |
| #define AOSS_CC_BASE 0x0C2A0000 |
Definition at line 6 of file addressmap.h.
| #define DISP_CC_BASE 0x0AF00000 |
Definition at line 14 of file addressmap.h.
| #define GCC_BASE 0x00100000 |
Definition at line 7 of file addressmap.h.
| #define GPIO_FUNC_QSPI_CLK GPIO63_FUNC_QSPI_CLK |
Definition at line 57 of file addressmap.h.
| #define GPIO_FUNC_QSPI_DATA_0 GPIO64_FUNC_QSPI_DATA_0 |
Definition at line 55 of file addressmap.h.
| #define GPIO_FUNC_QSPI_DATA_1 GPIO65_FUNC_QSPI_DATA_1 |
Definition at line 56 of file addressmap.h.
| #define L3_PLL_BASE 0x18284000 |
Definition at line 13 of file addressmap.h.
| #define QFPROM_BASE 0x00780000 |
Definition at line 40 of file addressmap.h.
| #define QMP_PHY_PCS_REG_BASE 0x088e9c00 |
Definition at line 46 of file addressmap.h.
| #define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 |
Definition at line 43 of file addressmap.h.
| #define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 |
Definition at line 45 of file addressmap.h.
| #define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 |
Definition at line 44 of file addressmap.h.
| #define QSPI_BASE 0x088DC000 |
Definition at line 8 of file addressmap.h.
| #define QSPI_CLK GPIO(63) |
Definition at line 50 of file addressmap.h.
| #define QSPI_CS GPIO(68) |
Definition at line 53 of file addressmap.h.
| #define QSPI_DATA_0 GPIO(64) |
Definition at line 51 of file addressmap.h.
| #define QSPI_DATA_1 GPIO(65) |
Definition at line 52 of file addressmap.h.
| #define QUP_SERIAL0_BASE 0x00880000 |
Definition at line 20 of file addressmap.h.
| #define QUP_SERIAL10_BASE 0x00A90000 |
Definition at line 33 of file addressmap.h.
| #define QUP_SERIAL11_BASE 0x00A94000 |
Definition at line 34 of file addressmap.h.
| #define QUP_SERIAL1_BASE 0x00884000 |
Definition at line 21 of file addressmap.h.
| #define QUP_SERIAL2_BASE 0x00888000 |
Definition at line 22 of file addressmap.h.
| #define QUP_SERIAL3_BASE 0x0088C000 |
Definition at line 23 of file addressmap.h.
| #define QUP_SERIAL4_BASE 0x00890000 |
Definition at line 24 of file addressmap.h.
| #define QUP_SERIAL5_BASE 0x00894000 |
Definition at line 25 of file addressmap.h.
| #define QUP_SERIAL6_BASE 0x00A80000 |
Definition at line 29 of file addressmap.h.
| #define QUP_SERIAL7_BASE 0x00A84000 |
Definition at line 30 of file addressmap.h.
| #define QUP_SERIAL8_BASE 0x00A88000 |
Definition at line 31 of file addressmap.h.
| #define QUP_SERIAL9_BASE 0x00A8C000 |
Definition at line 32 of file addressmap.h.
| #define QUP_WRAP0_BASE 0x008C0000 |
Definition at line 26 of file addressmap.h.
| #define QUP_WRAP1_BASE 0x00AC0000 |
Definition at line 35 of file addressmap.h.
| #define QUSB_PRIM_PHY_BASE 0x088e3000 |
Definition at line 41 of file addressmap.h.
| #define QUSB_PRIM_PHY_DIG_BASE 0x088e3200 |
Definition at line 42 of file addressmap.h.
| #define SDC1_TLMM_CFG_ADDR 0x03D7A000 |
Definition at line 60 of file addressmap.h.
| #define SDC2_TLMM_CFG_ADDR 0x03D7B000 |
Definition at line 61 of file addressmap.h.
| #define SILVER_PLL_BASE 0x18280000 |
Definition at line 12 of file addressmap.h.
| #define TLMM_NORTH_TILE_BASE 0x03900000 |
Definition at line 9 of file addressmap.h.
| #define TLMM_SOUTH_TILE_BASE 0x03D00000 |
Definition at line 10 of file addressmap.h.
| #define TLMM_WEST_TILE_BASE 0x03500000 |
Definition at line 11 of file addressmap.h.
| #define USB_HOST_DWC3_BASE 0x0a60c100 |
Definition at line 47 of file addressmap.h.
1.9.1