coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
port_descriptors.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <soc/gpio.h>
4 #include <soc/platform_descriptors.h>
5 #include <types.h>
6 #include <amdblocks/cpu.h>
7 
8 static const fsp_dxio_descriptor majolica_dxio_descriptors[] = {
9  { /* MXM */
10  .engine_type = PCIE_ENGINE,
11  .port_present = true,
12  .start_logical_lane = 16,
13  .end_logical_lane = 23,
14  .device_number = 1,
15  .function_number = 1,
16  .turn_off_unused_lanes = true,
17  .clk_req = CLK_REQ0,
18  .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
19  },
20  { /* SSD */
21  .engine_type = PCIE_ENGINE,
22  .port_present = true,
23  .start_logical_lane = 0,
24  .end_logical_lane = 1,
25  .device_number = 2,
26  .function_number = 1,
27  .turn_off_unused_lanes = true,
28  .clk_req = CLK_REQ5,
29  .gpio_group_id = GPIO_40,
30  .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
31  },
32  { /* DT */
33  .engine_type = PCIE_ENGINE,
34  .port_present = true,
35  .start_logical_lane = 4,
36  .end_logical_lane = 4,
37  .device_number = 2,
38  .function_number = 2,
39  .turn_off_unused_lanes = true,
40  .clk_req = CLK_REQ4_GFX,
41  .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
42  },
43  { /* WWAN */
44  .engine_type = PCIE_ENGINE,
45  .port_present = true,
46  .start_logical_lane = 5,
47  .end_logical_lane = 5,
48  .device_number = 2,
49  .function_number = 3,
50  .turn_off_unused_lanes = true,
51  .clk_req = CLK_REQ2,
52  .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
53  },
54  { /* LAN */
55  .engine_type = PCIE_ENGINE,
56  .port_present = true,
57  .start_logical_lane = 6,
58  .end_logical_lane = 6,
59  .device_number = 2,
60  .function_number = 4,
61  .turn_off_unused_lanes = true,
62  .clk_req = CLK_REQ1,
63  .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
64  },
65  { /* WLAN */
66  .engine_type = PCIE_ENGINE,
67  .port_present = true,
68  .start_logical_lane = 7,
69  .end_logical_lane = 7,
70  .device_number = 2,
71  .function_number = 5,
72  .turn_off_unused_lanes = true,
73  .clk_req = CLK_REQ6,
74  .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
75  },
76  { /* TB */
77  .engine_type = PCIE_ENGINE,
78  .port_present = true,
79  .start_logical_lane = 8,
80  .end_logical_lane = 11,
81  .device_number = 2,
82  .function_number = 6,
83  .turn_off_unused_lanes = true,
84  .clk_req = CLK_REQ3,
85  .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
86  },
87  { /* SATA */
88  .engine_type = SATA_ENGINE,
89  .port_present = true,
90  .start_logical_lane = 2,
91  .end_logical_lane = 3,
92  .channel_type = SATA_CHANNEL_LONG,
93  }
94 };
95 
96 static fsp_ddi_descriptor majolica_ddi_descriptors[] = {
97  { /* DDI0 - DP */
98  .connector_type = DDI_DP,
99  .aux_index = DDI_AUX1,
100  .hdp_index = DDI_HDP1
101  },
102  { /* DDI1 - HDMI */
103  .connector_type = DDI_HDMI,
104  .aux_index = DDI_AUX2,
105  .hdp_index = DDI_HDP2
106  },
107  { /* DDI2 */
108  .connector_type = DDI_UNUSED_TYPE,
109  .aux_index = DDI_AUX3,
110  .hdp_index = DDI_HDP3,
111  },
112  { /* DDI3 - DP (type C) */
113  .connector_type = DDI_DP,
114  .aux_index = DDI_AUX3,
115  .hdp_index = DDI_HDP3,
116  },
117  { /* DDI4 - DP (type C) */
118  .connector_type = DDI_DP,
119  .aux_index = DDI_AUX4,
120  .hdp_index = DDI_HDP4,
121  }
122 };
123 
124 void mainboard_get_dxio_ddi_descriptors(
125  const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
126  const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
127 {
128  if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2)
129  majolica_ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE;
130 
131  *dxio_descs = majolica_dxio_descriptors;
132  *dxio_num = ARRAY_SIZE(majolica_dxio_descriptors);
133  *ddi_descs = majolica_ddi_descriptors;
134  *ddi_num = ARRAY_SIZE(majolica_ddi_descriptors);
135 }
mainboard_get_dxio_ddi_descriptors
void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
Definition: port_descriptors.c:77
majolica_dxio_descriptors
static const fsp_dxio_descriptor majolica_dxio_descriptors[]
Definition: port_descriptors.c:8
majolica_ddi_descriptors
static fsp_ddi_descriptor majolica_ddi_descriptors[]
Definition: port_descriptors.c:96
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition: helpers.h:12
get_cpu_count
static int get_cpu_count(void)
Definition: haswell_init.c:584
GPIO_40
#define GPIO_40
Definition: gpio.h:49
get_threads_per_core
unsigned int get_threads_per_core(void)
Definition: cpu.c:15