coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
xhci.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef BAYTRAIL_XHCI_H
4 #define BAYTRAIL_XHCI_H
5 
6 /* XHCI PCI Registers */
7 #define XHCI_PWR_CTL_STS 0x74
8 #define XHCI_USB2PR 0xd0
9 #define XHCI_USB2PRM 0xd4
10 #define XHCI_USB3PR 0xd8
11 #define XHCI_USB3PRM 0xdc
12 #define XHCI_USB2PDO 0xe4
13 #define XHCI_USB3PDO 0xe8
14 
15 /* XHCI Memory Registers */
16 #define XHCI_USB3_PORTSC(port) (0x4e0 + (port * 0x10))
17 # define XHCI_USB3_PORTSC_CHST (0x7f << 17)
18 # define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
19 # define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
20 # define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */
21 # define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
22 # define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
23 # define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
24 # define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
25 # define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
26 # define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
27 # define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */
28 # define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
29 # define XHCI_PLSW_ENABLE (5 << 5) /* Enable port */
30 
31 /* The Fuse register is incorrect for Baytrail-M so use hardcoded values */
32 #define BYTM_USB2_PORT_COUNT 4
33 #define BYTM_USB2_PORT_MAP 0xf
34 #define BYTM_USB3_PORT_COUNT 1
35 #define BYTM_USB3_PORT_MAP 0x1
36 
37 #define XHCI_RESET_TIMEOUT 100000 /* 100ms */
38 
39 #endif /* BAYTRAIL_XHCI_H */