Macros
#define	XHCI_PWR_CTL_STS 0x74

#define	XHCI_USB2PR 0xd0

#define	XHCI_USB2PRM 0xd4

#define	XHCI_USB3PR 0xd8

#define	XHCI_USB3PRM 0xdc

#define	XHCI_USB2PDO 0xe4

#define	XHCI_USB3PDO 0xe8

#define	XHCI_USB3_PORTSC(port) (0x4e0 + (port * 0x10))

#define	XHCI_USB3_PORTSC_CHST (0x7f << 17)

#define	XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */

#define	XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */

#define	XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */

#define	XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */

#define	XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */

#define	XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */

#define	XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */

#define	XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */

#define	XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */

#define	XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */

#define	XHCI_PLSR_POLLING (7 << 5) /* Port is polling */

#define	XHCI_PLSW_ENABLE (5 << 5) /* Enable port */

#define	BYTM_USB2_PORT_COUNT 4

#define	BYTM_USB2_PORT_MAP 0xf

#define	BYTM_USB3_PORT_COUNT 1

#define	BYTM_USB3_PORT_MAP 0x1

#define	XHCI_RESET_TIMEOUT 100000 /* 100ms */

Macro Definition Documentation

◆ BYTM_USB2_PORT_COUNT

#define BYTM_USB2_PORT_COUNT 4

Definition at line 32 of file xhci.h.

◆ BYTM_USB2_PORT_MAP

#define BYTM_USB2_PORT_MAP 0xf

Definition at line 33 of file xhci.h.

◆ BYTM_USB3_PORT_COUNT

#define BYTM_USB3_PORT_COUNT 1

Definition at line 34 of file xhci.h.

◆ BYTM_USB3_PORT_MAP

#define BYTM_USB3_PORT_MAP 0x1

Definition at line 35 of file xhci.h.

◆ XHCI_PLSR_DISABLED

#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */

Definition at line 26 of file xhci.h.

◆ XHCI_PLSR_POLLING

#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */

Definition at line 28 of file xhci.h.

◆ XHCI_PLSR_RXDETECT

#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */

Definition at line 27 of file xhci.h.

◆ XHCI_PLSW_ENABLE

#define XHCI_PLSW_ENABLE (5 << 5) /* Enable port */

Definition at line 29 of file xhci.h.

◆ XHCI_PWR_CTL_STS

#define XHCI_PWR_CTL_STS 0x74

Definition at line 7 of file xhci.h.

◆ XHCI_RESET_TIMEOUT

#define XHCI_RESET_TIMEOUT 100000 /* 100ms */

Definition at line 37 of file xhci.h.

◆ XHCI_USB2PDO

#define XHCI_USB2PDO 0xe4

Definition at line 12 of file xhci.h.

◆ XHCI_USB2PR

#define XHCI_USB2PR 0xd0

Definition at line 8 of file xhci.h.

◆ XHCI_USB2PRM

#define XHCI_USB2PRM 0xd4

Definition at line 9 of file xhci.h.

◆ XHCI_USB3_PORTSC

#define XHCI_USB3_PORTSC ( port ) (0x4e0 + (port * 0x10))

Definition at line 16 of file xhci.h.

◆ XHCI_USB3_PORTSC_CHST

#define XHCI_USB3_PORTSC_CHST (0x7f << 17)

Definition at line 17 of file xhci.h.

◆ XHCI_USB3_PORTSC_LWS

#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */

Definition at line 22 of file xhci.h.

◆ XHCI_USB3_PORTSC_PED

#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */

Definition at line 23 of file xhci.h.

◆ XHCI_USB3_PORTSC_PLS

#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */

Definition at line 25 of file xhci.h.

◆ XHCI_USB3_PORTSC_WCE

#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */

Definition at line 18 of file xhci.h.

◆ XHCI_USB3_PORTSC_WDE

#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */

Definition at line 19 of file xhci.h.

◆ XHCI_USB3_PORTSC_WOE

#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */

Definition at line 20 of file xhci.h.

◆ XHCI_USB3_PORTSC_WPR

#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */

Definition at line 24 of file xhci.h.

◆ XHCI_USB3_PORTSC_WRC

#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */

Definition at line 21 of file xhci.h.

◆ XHCI_USB3PDO

#define XHCI_USB3PDO 0xe8

Definition at line 13 of file xhci.h.

◆ XHCI_USB3PR

#define XHCI_USB3PR 0xd8

Definition at line 10 of file xhci.h.

◆ XHCI_USB3PRM

#define XHCI_USB3PRM 0xdc

Definition at line 11 of file xhci.h.

Macros