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ddr3.h File Reference
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Macros

#define MT41K256M16HA125E_EMIF_READ_LATENCY   0x100007
 
#define MT41K256M16HA125E_EMIF_TIM1   0x0AAAD4DB
 
#define MT41K256M16HA125E_EMIF_TIM2   0x266B7FDA
 
#define MT41K256M16HA125E_EMIF_TIM3   0x501F867F
 
#define MT41K256M16HA125E_EMIF_SDCFG   0x61C05332
 
#define MT41K256M16HA125E_EMIF_SDREF   0xC30
 
#define MT41K256M16HA125E_ZQ_CFG   0x50074BE4
 
#define MT41K256M16HA125E_RATIO   0x80
 
#define MT41K256M16HA125E_INVERT_CLKOUT   0x0
 
#define MT41K256M16HA125E_RD_DQS   0x38
 
#define MT41K256M16HA125E_WR_DQS   0x44
 
#define MT41K256M16HA125E_PHY_WR_DATA   0x7D
 
#define MT41K256M16HA125E_PHY_FIFO_WE   0x94
 
#define MT41K256M16HA125E_IOCTRL_VALUE   0x18B
 
#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK   0x00141414
 

Macro Definition Documentation

◆ EMIF_OCP_CONFIG_BEAGLEBONE_BLACK

#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK   0x00141414

Definition at line 27 of file ddr3.h.

◆ MT41K256M16HA125E_EMIF_READ_LATENCY

#define MT41K256M16HA125E_EMIF_READ_LATENCY   0x100007

Definition at line 12 of file ddr3.h.

◆ MT41K256M16HA125E_EMIF_SDCFG

#define MT41K256M16HA125E_EMIF_SDCFG   0x61C05332

Definition at line 16 of file ddr3.h.

◆ MT41K256M16HA125E_EMIF_SDREF

#define MT41K256M16HA125E_EMIF_SDREF   0xC30

Definition at line 17 of file ddr3.h.

◆ MT41K256M16HA125E_EMIF_TIM1

#define MT41K256M16HA125E_EMIF_TIM1   0x0AAAD4DB

Definition at line 13 of file ddr3.h.

◆ MT41K256M16HA125E_EMIF_TIM2

#define MT41K256M16HA125E_EMIF_TIM2   0x266B7FDA

Definition at line 14 of file ddr3.h.

◆ MT41K256M16HA125E_EMIF_TIM3

#define MT41K256M16HA125E_EMIF_TIM3   0x501F867F

Definition at line 15 of file ddr3.h.

◆ MT41K256M16HA125E_INVERT_CLKOUT

#define MT41K256M16HA125E_INVERT_CLKOUT   0x0

Definition at line 20 of file ddr3.h.

◆ MT41K256M16HA125E_IOCTRL_VALUE

#define MT41K256M16HA125E_IOCTRL_VALUE   0x18B

Definition at line 25 of file ddr3.h.

◆ MT41K256M16HA125E_PHY_FIFO_WE

#define MT41K256M16HA125E_PHY_FIFO_WE   0x94

Definition at line 24 of file ddr3.h.

◆ MT41K256M16HA125E_PHY_WR_DATA

#define MT41K256M16HA125E_PHY_WR_DATA   0x7D

Definition at line 23 of file ddr3.h.

◆ MT41K256M16HA125E_RATIO

#define MT41K256M16HA125E_RATIO   0x80

Definition at line 19 of file ddr3.h.

◆ MT41K256M16HA125E_RD_DQS

#define MT41K256M16HA125E_RD_DQS   0x38

Definition at line 21 of file ddr3.h.

◆ MT41K256M16HA125E_WR_DQS

#define MT41K256M16HA125E_WR_DQS   0x44

Definition at line 22 of file ddr3.h.

◆ MT41K256M16HA125E_ZQ_CFG

#define MT41K256M16HA125E_ZQ_CFG   0x50074BE4

Definition at line 18 of file ddr3.h.