coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
nvs.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef SOUTHBRIDGE_INTEL_I82801IX_NVS_H
4 #define SOUTHBRIDGE_INTEL_I82801IX_NVS_H
5 
6 #include <stdint.h>
7 
8 struct __packed global_nvs {
9  /* Miscellaneous */
10  u16 unused_was_osys; /* 0x00 - Operating System */
11  u8 smif; /* 0x02 - SMI function call ("TRAP") */
12  u8 unused_was_prm0; /* 0x03 - SMI function call parameter */
13  u8 unused_was_prm1; /* 0x04 - SMI function call parameter */
14  u8 scif; /* 0x05 - SCI function call (via _L00) */
15  u8 unused_was_prm2; /* 0x06 - SCI function call parameter */
16  u8 unused_was_prm3; /* 0x07 - SCI function call parameter */
17  u8 unused_was_lckf; /* 0x08 - Global Lock function for EC */
18  u8 unused_was_prm4; /* 0x09 - Lock function parameter */
19  u8 unused_was_prm5; /* 0x0a - Lock function parameter */
20  u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
21  u8 lids; /* 0x0f - LID state (open = 1) */
22  u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
23  u8 dbgs; /* 0x11 - Debug state */
24  u8 linx; /* 0x12 - Linux OS */
25  u8 dckn; /* 0x13 - PCIe docking state */
26  /* Thermal policy */
27  u8 actt; /* 0x14 - active trip point */
28  u8 tpsv; /* 0x15 - passive trip point */
29  u8 tc1v; /* 0x16 - passive trip point TC1 */
30  u8 tc2v; /* 0x17 - passive trip point TC2 */
31  u8 tspv; /* 0x18 - passive trip point TSP */
32  u8 tcrt; /* 0x19 - critical trip point */
33  u8 dtse; /* 0x1a - Digital Thermal Sensor enable */
34  u8 dts1; /* 0x1b - DT sensor 1 */
35  u8 flvl; /* 0x1c - current fan level */
36  u8 rsvd2;
37  /* Battery Support */
38  u8 bnum; /* 0x1e - number of batteries */
39  u8 b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */
40  u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
41  u8 rsvd3[3];
42  /* Processor Identification */
43  u8 unused_was_apic; /* 0x28 - APIC enabled */
44  u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
45  u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
46  u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
47  u8 ppcm; /* 0x2c - Max. PPC state */
48  u8 rsvd4[5];
49  /* Super I/O & CMOS config */
50  u8 natp; /* 0x32 - SIO type */
51  u8 cmap; /* 0x33 - */
52  u8 cmbp; /* 0x34 - */
53  u8 lptp; /* 0x35 - LPT port */
54  u8 fdcp; /* 0x36 - Floppy Disk Controller */
55  u8 rfdv; /* 0x37 - */
56  u8 hotk; /* 0x38 - Hot Key */
57  u8 rtcf;
58  u8 util;
59  u8 acin;
60  /* Integrated Graphics Device */
61  u8 igds; /* 0x3c - IGD state */
62  u8 tlst; /* 0x3d - Display Toggle List Pointer */
63  u8 cadl; /* 0x3e - currently attached devices */
64  u8 padl; /* 0x3f - previously attached devices */
65  u8 rsvd5[36];
66  /* Backlight Control */
67  u8 blcs; /* 0x64 - Backlight Control possible */
68  u8 brtl;
69  u8 odds;
70  u8 rsvd6[0x7];
71  /* Ambient Light Sensors*/
72  u8 alse; /* 0x6e - ALS enable */
73  u8 alaf;
74  u8 llow;
75  u8 lhih;
76  u8 rsvd7[0x6];
77  /* EMA */
78  u8 emae; /* 0x78 - EMA enable */
79  u16 emap;
80  u16 emal;
81  u8 rsvd8[0x5];
82  /* MEF */
83  u8 mefe; /* 0x82 - MEF enable */
84  u8 rsvd9[0x9];
85  /* TPM support */
86  u8 tpmp; /* 0x8c - TPM */
87  u8 tpme;
88  u8 rsvd10[8];
89  /* SATA */
90  u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
91  u8 gtf1[7];
92  u8 gtf2[7];
93  u8 idem;
94  u8 idet;
95  u8 rsvd11[67];
96  /* Mainboard specific */
97  u8 dock; /* 0xf0 - Docking Status */
98  u8 bten;
99 
100  u32 cbmc;
101 
102  /* Required for future unified acpi_save_wake_source. */
103  u32 pm1i;
104  u32 gpei;
105 };
106 
107 #endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */
u32
uint32_t u32
Definition: stdint.h:51
u16
uint16_t u16
Definition: stdint.h:48
u8
uint8_t u8
Definition: stdint.h:45
__packed
Definition: x86.c:23
__packed::cadl
u32 cadl
Definition: opregion.h:72
global_nvs
Definition: nvs.h:14