coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
hpet.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
arch/hpet.h
>
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#include <
southbridge/intel/common/rcba.h
>
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#include <
stdint.h
>
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#include "
hpet.h
"
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#define HPTC 0x3404
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#define HPET32(x) (*((volatile u32 *)(HPET_BASE_ADDRESS + (x))))
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void
enable_hpet
(
void
)
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{
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u32
reg32;
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reg32 =
RCBA32
(
HPTC
);
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reg32 &= ~0x03;
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reg32 |= (1 << 7);
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RCBA32
(
HPTC
) = reg32;
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/* Read back for posted write to take effect */
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RCBA32
(
HPTC
);
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HPET32
(0x10) =
HPET32
(0x10) | 1;
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}
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void
hpet_udelay
(
u32
delay
)
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{
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u32
start, finish, now;
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delay
*= 15;
/* now in usec */
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start =
HPET32
(0xf0);
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finish = start +
delay
;
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while
(1) {
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now =
HPET32
(0xf0);
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if
(finish > start) {
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if
(now >= finish)
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break
;
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}
else
{
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if
((now < start) && (now >= finish))
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break
;
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}
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}
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}
hpet.h
delay
void delay(unsigned int secs)
Definition:
delay.c:8
HPET32
#define HPET32(x)
Definition:
hpet.c:11
HPTC
#define HPTC
Definition:
hpet.c:9
enable_hpet
void enable_hpet(void)
Definition:
hpet.c:13
hpet_udelay
void hpet_udelay(u32 delay)
Definition:
hpet.c:25
hpet.h
rcba.h
RCBA32
#define RCBA32(x)
Definition:
rcba.h:14
stdint.h
u32
uint32_t u32
Definition:
stdint.h:51
src
southbridge
intel
common
hpet.c
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