6 #ifndef __SOC_QUALCOMM_IPQ806X_EBI2_H_
7 #define __SOC_QUALCOMM_IPQ806X_EBI2_H_
11 #define EBI2CR_BASE (0x1A600000)
34 #define CS7_CFG_MASK 0x00001000
35 #define CS7_CFG_DISABLE 0x00000000
36 #define CS7_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00001000
37 #define CS7_CFG(i) ((i) << 12)
39 #define CS6_CFG_MASK 0x00000800
40 #define CS6_CFG_DISABLE 0x00000000
41 #define CS6_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000800
42 #define CS6_CFG(i) ((i) << 11)
44 #define ETM_CS_CFG_MASK 0x00000400
45 #define ETM_CS_CFG_DISABLE 0x00000000
46 #define ETM_CS_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000400
47 #define ETM_CS_CFG(i) ((i) << 10)
49 #define CS5_CFG_MASK 0x00000300
50 #define CS5_CFG_DISABLE 0x00000000
51 #define CS5_CFG_LCD_DEVICE_CONNECTED 0x00000100
52 #define CS5_CFG_LCD_DEVICE_CHIP_ENABLE 0x00000200
53 #define CS5_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000300
54 #define CS5_CFG(i) ((i) << 8)
56 #define CS4_CFG_MASK 0x000000c0
57 #define CS4_CFG_DISABLE 0x00000000
58 #define CS4_CFG_LCD_DEVICE_CONNECTED 0x00000040
59 #define CS4_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x000000C0
60 #define CS4_CFG(i) ((i) << 6)
62 #define CS3_CFG_MASK 0x00000020
63 #define CS3_CFG_DISABLE 0x00000000
64 #define CS3_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000020
65 #define CS3_CFG(i) ((i) << 5)
67 #define CS2_CFG_MASK 0x00000010
68 #define CS2_CFG_DISABLE 0x00000000
69 #define CS2_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000010
70 #define CS2_CFG(i) ((i) << 4)
72 #define CS1_CFG_MASK 0x0000000c
73 #define CS1_CFG_DISABLE 0x00000000
74 #define CS1_CFG_SERIAL_FLASH_DEVICE 0x00000004
75 #define CS1_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000008
76 #define CS1_CFG(i) ((i) << 2)
78 #define CS0_CFG_MASK 0x00000003
79 #define CS0_CFG_DISABLE 0x00000000
80 #define CS0_CFG_SERIAL_FLASH_DEVICE 0x00000001
81 #define CS0_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000002
82 #define CS0_CFG(i) ((i) << 0)
uint32_t chip_select_cfg0
uint32_t crc_reminder_cfg
uint32_t mutex_addr_offset