coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
reg_script.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef REG_SCRIPT_H
4 #define REG_SCRIPT_H
5 
6 #include <stdint.h>
7 #include <device/device.h>
8 #include <device/pci_type.h>
9 #include <device/resource.h>
10 
11 /*
12  * The reg script library is a way to provide data-driven I/O accesses for
13  * initializing devices. It currently supports PCI, legacy I/O,
14  * memory-mapped I/O, and IOSF accesses.
15  *
16  * In order to simplify things for the developer the following features
17  * are employed:
18  * - Chaining of tables that allow runtime tables to chain to compile-time
19  * tables.
20  *
21  * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push
22  * and pop of the context. A chained reg_script inherits the previous
23  * context (such as current device), but it does not impact the previous
24  * context in any way.
25  */
26 
27 enum {
28  REG_SCRIPT_COMMAND_READ,
29  REG_SCRIPT_COMMAND_WRITE,
30  REG_SCRIPT_COMMAND_RMW,
31  REG_SCRIPT_COMMAND_RXW,
32  REG_SCRIPT_COMMAND_POLL,
33  REG_SCRIPT_COMMAND_SET_DEV,
34  REG_SCRIPT_COMMAND_NEXT,
35  REG_SCRIPT_COMMAND_DISPLAY,
36 
37  /* Insert new types above this comment */
38 
39  REG_SCRIPT_COMMAND_END,
40 };
41 
42 enum {
43  REG_SCRIPT_TYPE_PCI,
44  REG_SCRIPT_TYPE_IO,
45  REG_SCRIPT_TYPE_MMIO,
46  REG_SCRIPT_TYPE_RES,
47  REG_SCRIPT_TYPE_IOSF,
48  REG_SCRIPT_TYPE_MSR,
49 
50  /* Insert other platform independent values above this comment */
51 
52  REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000,
53  REG_SCRIPT_TYPE_SOC_BASE = REG_SCRIPT_TYPE_PLATFORM_BASE,
54  REG_SCRIPT_TYPE_MAINBOARD_BASE = 0x20000
55 };
56 
57 enum {
58  REG_SCRIPT_SIZE_8,
59  REG_SCRIPT_SIZE_16,
60  REG_SCRIPT_SIZE_32,
61  REG_SCRIPT_SIZE_64,
62 };
63 
64 struct reg_script {
65  uint32_t command;
66  uint32_t type;
67  uint32_t size;
68  uint32_t reg;
69  uint64_t mask;
70  uint64_t value;
71  uint32_t timeout;
72  union {
73  uint32_t id;
74  const struct reg_script *next;
75 #ifdef __SIMPLE_DEVICE__
76  pci_devfn_t dev;
77 #else
78  struct device *dev;
79 #endif
80  unsigned int res_index;
81  };
82 };
83 
84 struct reg_script_context {
85 #ifdef __SIMPLE_DEVICE__
86  pci_devfn_t dev;
87 #else
88  struct device *dev;
89 #endif
90  struct resource *res;
91  const struct reg_script *step;
92  uint8_t display_state; /* Only modified by reg_script_run_step */
93  uint8_t display_features; /* Step routine modifies to control display */
94  const char *display_prefix; /* Prefix tag to display */
95 };
96 
97 struct reg_script_bus_entry {
98  uint32_t type;
99  uint64_t (*reg_script_read)(struct reg_script_context *ctx);
100  void (*reg_script_write)(struct reg_script_context *ctx);
101 };
102 
103 #define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__((used, section(".rsbe_init")))
104 
105 #define REG_SCRIPT_BUS_ENTRY(bus_entry_) \
106  const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \
107  REG_SCRIPT_TABLE_ATTRIBUTE = &bus_entry_;
108 
109 /* Internal helper Macros. */
110 
111 #define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \
112  mask_, value_, timeout_, id_) \
113  { .command = cmd_, \
114  .type = type_, \
115  .size = size_, \
116  .reg = reg_, \
117  .mask = mask_, \
118  .value = value_, \
119  .timeout = timeout_, \
120  .id = id_, \
121  }
122 
123 #define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \
124  mask_, value_, timeout_) \
125  { .command = cmd_, \
126  .type = type_, \
127  .size = size_, \
128  .reg = reg_, \
129  .mask = mask_, \
130  .value = value_, \
131  .timeout = timeout_, \
132  .res_index = res_index_, \
133  }
134 
135 /* Display control */
136 #define REG_SCRIPT_DISPLAY_ALL 0xff
137 #define REG_SCRIPT_DISPLAY_REGISTER 0x02
138 #define REG_SCRIPT_DISPLAY_VALUE 0x01
139 #define REG_SCRIPT_DISPLAY_NOTHING 0
140 
141 #define REG_SCRIPT_DISPLAY_OFF \
142  { .command = REG_SCRIPT_COMMAND_DISPLAY, \
143  .value = REG_SCRIPT_DISPLAY_NOTHING, \
144  }
145 #define REG_SCRIPT_DISPLAY_ON \
146  { .command = REG_SCRIPT_COMMAND_DISPLAY, \
147  .value = REG_SCRIPT_DISPLAY_ALL, \
148  }
149 
150 /*
151  * PCI
152  */
153 
154 #define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \
155  _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
156  REG_SCRIPT_TYPE_PCI, \
157  REG_SCRIPT_SIZE_##bits_, \
158  reg_, mask_, value_, timeout_, 0)
159 #define REG_PCI_READ8(reg_) \
160  REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0)
161 #define REG_PCI_READ16(reg_) \
162  REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0)
163 #define REG_PCI_READ32(reg_) \
164  REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0)
165 #define REG_PCI_WRITE8(reg_, value_) \
166  REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0)
167 #define REG_PCI_WRITE16(reg_, value_) \
168  REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0)
169 #define REG_PCI_WRITE32(reg_, value_) \
170  REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0)
171 #define REG_PCI_RMW8(reg_, mask_, value_) \
172  REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0)
173 #define REG_PCI_RMW16(reg_, mask_, value_) \
174  REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0)
175 #define REG_PCI_RMW32(reg_, mask_, value_) \
176  REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0)
177 #define REG_PCI_RXW8(reg_, mask_, value_) \
178  REG_SCRIPT_PCI(RXW, 8, reg_, mask_, value_, 0)
179 #define REG_PCI_RXW16(reg_, mask_, value_) \
180  REG_SCRIPT_PCI(RXW, 16, reg_, mask_, value_, 0)
181 #define REG_PCI_RXW32(reg_, mask_, value_) \
182  REG_SCRIPT_PCI(RXW, 32, reg_, mask_, value_, 0)
183 #define REG_PCI_OR8(reg_, value_) \
184  REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0)
185 #define REG_PCI_OR16(reg_, value_) \
186  REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0)
187 #define REG_PCI_OR32(reg_, value_) \
188  REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0)
189 #define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \
190  REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_)
191 #define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \
192  REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_)
193 #define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \
194  REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_)
195 #define REG_PCI_XOR8(reg_, value_) \
196  REG_SCRIPT_PCI(RXW, 8, reg_, 0xff, value_, 0)
197 #define REG_PCI_XOR16(reg_, value_) \
198  REG_SCRIPT_PCI(RXW, 16, reg_, 0xffff, value_, 0)
199 #define REG_PCI_XOR32(reg_, value_) \
200  REG_SCRIPT_PCI(RXW, 32, reg_, 0xffffffff, value_, 0)
201 
202 /*
203  * Legacy IO
204  */
205 
206 #define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \
207  _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
208  REG_SCRIPT_TYPE_IO, \
209  REG_SCRIPT_SIZE_##bits_, \
210  reg_, mask_, value_, timeout_, 0)
211 #define REG_IO_READ8(reg_) \
212  REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0)
213 #define REG_IO_READ16(reg_) \
214  REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0)
215 #define REG_IO_READ32(reg_) \
216  REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0)
217 #define REG_IO_WRITE8(reg_, value_) \
218  REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0)
219 #define REG_IO_WRITE16(reg_, value_) \
220  REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0)
221 #define REG_IO_WRITE32(reg_, value_) \
222  REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0)
223 #define REG_IO_RMW8(reg_, mask_, value_) \
224  REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0)
225 #define REG_IO_RMW16(reg_, mask_, value_) \
226  REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0)
227 #define REG_IO_RMW32(reg_, mask_, value_) \
228  REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0)
229 #define REG_IO_RXW8(reg_, mask_, value_) \
230  REG_SCRIPT_IO(RXW, 8, reg_, mask_, value_, 0)
231 #define REG_IO_RXW16(reg_, mask_, value_) \
232  REG_SCRIPT_IO(RXW, 16, reg_, mask_, value_, 0)
233 #define REG_IO_RXW32(reg_, mask_, value_) \
234  REG_SCRIPT_IO(RXW, 32, reg_, mask_, value_, 0)
235 #define REG_IO_OR8(reg_, value_) \
236  REG_IO_RMW8(reg_, 0xff, value_)
237 #define REG_IO_OR16(reg_, value_) \
238  REG_IO_RMW16(reg_, 0xffff, value_)
239 #define REG_IO_OR32(reg_, value_) \
240  REG_IO_RMW32(reg_, 0xffffffff, value_)
241 #define REG_IO_POLL8(reg_, mask_, value_, timeout_) \
242  REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_)
243 #define REG_IO_POLL16(reg_, mask_, value_, timeout_) \
244  REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_)
245 #define REG_IO_POLL32(reg_, mask_, value_, timeout_) \
246  REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_)
247 #define REG_IO_XOR8(reg_, value_) \
248  REG_IO_RXW8(reg_, 0xff, value_)
249 #define REG_IO_XOR16(reg_, value_) \
250  REG_IO_RXW16(reg_, 0xffff, value_)
251 #define REG_IO_XOR32(reg_, value_) \
252  REG_IO_RXW32(reg_, 0xffffffff, value_)
253 
254 /*
255  * Memory Mapped IO
256  */
257 
258 #define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \
259  _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
260  REG_SCRIPT_TYPE_MMIO, \
261  REG_SCRIPT_SIZE_##bits_, \
262  reg_, mask_, value_, timeout_, 0)
263 #define REG_MMIO_READ8(reg_) \
264  REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0)
265 #define REG_MMIO_READ16(reg_) \
266  REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0)
267 #define REG_MMIO_READ32(reg_) \
268  REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0)
269 #define REG_MMIO_WRITE8(reg_, value_) \
270  REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0)
271 #define REG_MMIO_WRITE16(reg_, value_) \
272  REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0)
273 #define REG_MMIO_WRITE32(reg_, value_) \
274  REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0)
275 #define REG_MMIO_RMW8(reg_, mask_, value_) \
276  REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0)
277 #define REG_MMIO_RMW16(reg_, mask_, value_) \
278  REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0)
279 #define REG_MMIO_RMW32(reg_, mask_, value_) \
280  REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0)
281 #define REG_MMIO_RXW8(reg_, mask_, value_) \
282  REG_SCRIPT_MMIO(RXW, 8, reg_, mask_, value_, 0)
283 #define REG_MMIO_RXW16(reg_, mask_, value_) \
284  REG_SCRIPT_MMIO(RXW, 16, reg_, mask_, value_, 0)
285 #define REG_MMIO_RXW32(reg_, mask_, value_) \
286  REG_SCRIPT_MMIO(RXW, 32, reg_, mask_, value_, 0)
287 #define REG_MMIO_OR8(reg_, value_) \
288  REG_MMIO_RMW8(reg_, 0xff, value_)
289 #define REG_MMIO_OR16(reg_, value_) \
290  REG_MMIO_RMW16(reg_, 0xffff, value_)
291 #define REG_MMIO_OR32(reg_, value_) \
292  REG_MMIO_RMW32(reg_, 0xffffffff, value_)
293 #define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \
294  REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_)
295 #define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \
296  REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_)
297 #define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \
298  REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_)
299 #define REG_MMIO_XOR8(reg_, value_) \
300  REG_MMIO_RXW8(reg_, 0xff, value_)
301 #define REG_MMIO_XOR16(reg_, value_) \
302  REG_MMIO_RXW16(reg_, 0xffff, value_)
303 #define REG_MMIO_XOR32(reg_, value_) \
304  REG_MMIO_RXW32(reg_, 0xffffffff, value_)
305 
306 /*
307  * Access through a device's resource such as a Base Address Register (BAR)
308  */
309 
310 #define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \
311  _REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_, \
312  REG_SCRIPT_TYPE_RES, bar_, \
313  REG_SCRIPT_SIZE_##bits_, \
314  reg_, mask_, value_, timeout_)
315 #define REG_RES_READ8(bar_, reg_) \
316  REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0)
317 #define REG_RES_READ16(bar_, reg_) \
318  REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0)
319 #define REG_RES_READ32(bar_, reg_) \
320  REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0)
321 #define REG_RES_WRITE8(bar_, reg_, value_) \
322  REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0)
323 #define REG_RES_WRITE16(bar_, reg_, value_) \
324  REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0)
325 #define REG_RES_WRITE32(bar_, reg_, value_) \
326  REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0)
327 #define REG_RES_RMW8(bar_, reg_, mask_, value_) \
328  REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0)
329 #define REG_RES_RMW16(bar_, reg_, mask_, value_) \
330  REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0)
331 #define REG_RES_RMW32(bar_, reg_, mask_, value_) \
332  REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0)
333 #define REG_RES_RXW8(bar_, reg_, mask_, value_) \
334  REG_SCRIPT_RES(RXW, 8, bar_, reg_, mask_, value_, 0)
335 #define REG_RES_RXW16(bar_, reg_, mask_, value_) \
336  REG_SCRIPT_RES(RXW, 16, bar_, reg_, mask_, value_, 0)
337 #define REG_RES_RXW32(bar_, reg_, mask_, value_) \
338  REG_SCRIPT_RES(RXW, 32, bar_, reg_, mask_, value_, 0)
339 #define REG_RES_OR8(bar_, reg_, value_) \
340  REG_RES_RMW8(bar_, reg_, 0xff, value_)
341 #define REG_RES_OR16(bar_, reg_, value_) \
342  REG_RES_RMW16(bar_, reg_, 0xffff, value_)
343 #define REG_RES_OR32(bar_, reg_, value_) \
344  REG_RES_RMW32(bar_, reg_, 0xffffffff, value_)
345 #define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \
346  REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_)
347 #define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \
348  REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_)
349 #define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \
350  REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_)
351 #define REG_RES_XOR8(bar_, reg_, value_) \
352  REG_RES_RXW8(bar_, reg_, 0xff, value_)
353 #define REG_RES_XOR16(bar_, reg_, value_) \
354  REG_RES_RXW16(bar_, reg_, 0xffff, value_)
355 #define REG_RES_XOR32(bar_, reg_, value_) \
356  REG_RES_RXW32(bar_, reg_, 0xffffffff, value_)
357 
358 #if CONFIG(SOC_INTEL_BAYTRAIL)
359 /*
360  * IO Sideband Function
361  */
362 
363 #define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \
364  _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
365  REG_SCRIPT_TYPE_IOSF, \
366  REG_SCRIPT_SIZE_32, \
367  reg_, mask_, value_, timeout_, unit_)
368 #define REG_IOSF_READ(unit_, reg_) \
369  REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0)
370 #define REG_IOSF_WRITE(unit_, reg_, value_) \
371  REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0)
372 #define REG_IOSF_RMW(unit_, reg_, mask_, value_) \
373  REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0)
374 #define REG_IOSF_RXW(unit_, reg_, mask_, value_) \
375  REG_SCRIPT_IOSF(RXW, unit_, reg_, mask_, value_, 0)
376 #define REG_IOSF_OR(unit_, reg_, value_) \
377  REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
378 #define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
379  REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
380 #define REG_IOSF_XOR(unit_, reg_, value_) \
381  REG_IOSF_RXW(unit_, reg_, 0xffffffff, value_)
382 #endif /* CONFIG_SOC_INTEL_BAYTRAIL */
383 
384 /*
385  * CPU Model Specific Register
386  */
387 
388 #define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \
389  _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
390  REG_SCRIPT_TYPE_MSR, \
391  REG_SCRIPT_SIZE_64, \
392  reg_, mask_, value_, timeout_, 0)
393 #define REG_MSR_READ(reg_) \
394  REG_SCRIPT_MSR(READ, reg_, 0, 0, 0)
395 #define REG_MSR_WRITE(reg_, value_) \
396  REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0)
397 #define REG_MSR_RMW(reg_, mask_, value_) \
398  REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0)
399 #define REG_MSR_RXW(reg_, mask_, value_) \
400  REG_SCRIPT_MSR(RXW, reg_, mask_, value_, 0)
401 #define REG_MSR_OR(reg_, value_) \
402  REG_MSR_RMW(reg_, -1ULL, value_)
403 #define REG_MSR_POLL(reg_, mask_, value_, timeout_) \
404  REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_)
405 #define REG_MSR_XOR(reg_, value_) \
406  REG_MSR_RXW(reg_, -1ULL, value_)
407 
408 /*
409  * Chain to another table.
410  */
411 #define REG_SCRIPT_NEXT(next_) \
412  { .command = REG_SCRIPT_COMMAND_NEXT, \
413  .next = next_, \
414  }
415 
416 /*
417  * Set current device
418  */
419 #define REG_SCRIPT_SET_DEV(dev_) \
420  { .command = REG_SCRIPT_COMMAND_SET_DEV, \
421  .dev = dev_, \
422  }
423 
424 /*
425  * Last script entry. All tables need to end with REG_SCRIPT_END.
426  */
427 #define REG_SCRIPT_END \
428  _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0)
429 
430 void reg_script_run(const struct reg_script *script);
431 #ifdef __SIMPLE_DEVICE__
432 void reg_script_run_on_dev(pci_devfn_t dev, const struct reg_script *step);
433 #else
434 void reg_script_run_on_dev(struct device *dev, const struct reg_script *step);
435 #endif
436 
437 #endif /* REG_SCRIPT_H */
pci_type.h
pci_devfn_t
u32 pci_devfn_t
Definition: pci_type.h:8
REG_SCRIPT_SIZE_8
@ REG_SCRIPT_SIZE_8
Definition: reg_script.h:58
REG_SCRIPT_SIZE_64
@ REG_SCRIPT_SIZE_64
Definition: reg_script.h:61
REG_SCRIPT_SIZE_16
@ REG_SCRIPT_SIZE_16
Definition: reg_script.h:59
REG_SCRIPT_SIZE_32
@ REG_SCRIPT_SIZE_32
Definition: reg_script.h:60
reg_script_run
void reg_script_run(const struct reg_script *script)
Definition: reg_script.c:700
reg_script_run_on_dev
void reg_script_run_on_dev(struct device *dev, const struct reg_script *step)
Definition: reg_script.c:689
REG_SCRIPT_TYPE_PCI
@ REG_SCRIPT_TYPE_PCI
Definition: reg_script.h:43
REG_SCRIPT_TYPE_MAINBOARD_BASE
@ REG_SCRIPT_TYPE_MAINBOARD_BASE
Definition: reg_script.h:54
REG_SCRIPT_TYPE_PLATFORM_BASE
@ REG_SCRIPT_TYPE_PLATFORM_BASE
Definition: reg_script.h:52
REG_SCRIPT_TYPE_SOC_BASE
@ REG_SCRIPT_TYPE_SOC_BASE
Definition: reg_script.h:53
REG_SCRIPT_TYPE_RES
@ REG_SCRIPT_TYPE_RES
Definition: reg_script.h:46
REG_SCRIPT_TYPE_MSR
@ REG_SCRIPT_TYPE_MSR
Definition: reg_script.h:48
REG_SCRIPT_TYPE_IO
@ REG_SCRIPT_TYPE_IO
Definition: reg_script.h:44
REG_SCRIPT_TYPE_MMIO
@ REG_SCRIPT_TYPE_MMIO
Definition: reg_script.h:45
REG_SCRIPT_TYPE_IOSF
@ REG_SCRIPT_TYPE_IOSF
Definition: reg_script.h:47
REG_SCRIPT_COMMAND_POLL
@ REG_SCRIPT_COMMAND_POLL
Definition: reg_script.h:32
REG_SCRIPT_COMMAND_DISPLAY
@ REG_SCRIPT_COMMAND_DISPLAY
Definition: reg_script.h:35
REG_SCRIPT_COMMAND_SET_DEV
@ REG_SCRIPT_COMMAND_SET_DEV
Definition: reg_script.h:33
REG_SCRIPT_COMMAND_END
@ REG_SCRIPT_COMMAND_END
Definition: reg_script.h:39
REG_SCRIPT_COMMAND_READ
@ REG_SCRIPT_COMMAND_READ
Definition: reg_script.h:28
REG_SCRIPT_COMMAND_NEXT
@ REG_SCRIPT_COMMAND_NEXT
Definition: reg_script.h:34
REG_SCRIPT_COMMAND_RMW
@ REG_SCRIPT_COMMAND_RMW
Definition: reg_script.h:30
REG_SCRIPT_COMMAND_WRITE
@ REG_SCRIPT_COMMAND_WRITE
Definition: reg_script.h:29
REG_SCRIPT_COMMAND_RXW
@ REG_SCRIPT_COMMAND_RXW
Definition: reg_script.h:31
uint32_t
unsigned int uint32_t
Definition: stdint.h:14
uint64_t
unsigned long long uint64_t
Definition: stdint.h:17
uint8_t
unsigned char uint8_t
Definition: stdint.h:8
device
Definition: device.h:107
reg_script_bus_entry
Definition: reg_script.h:97
reg_script_bus_entry::reg_script_read
uint64_t(* reg_script_read)(struct reg_script_context *ctx)
Definition: reg_script.h:99
reg_script_bus_entry::reg_script_write
void(* reg_script_write)(struct reg_script_context *ctx)
Definition: reg_script.h:100
reg_script_bus_entry::type
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Definition: reg_script.h:98
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Definition: reg_script.h:84
reg_script_context::display_state
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Definition: reg_script.h:92
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const struct reg_script * step
Definition: reg_script.h:91
reg_script_context::res
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Definition: reg_script.h:90
reg_script_context::display_prefix
const char * display_prefix
Definition: reg_script.h:94
reg_script_context::display_features
uint8_t display_features
Definition: reg_script.h:93
reg_script_context::dev
struct device * dev
Definition: reg_script.h:88
reg_script
Definition: reg_script.h:64
reg_script::res_index
unsigned int res_index
Definition: reg_script.h:80
reg_script::next
const struct reg_script * next
Definition: reg_script.h:74
reg_script::value
uint64_t value
Definition: reg_script.h:70
reg_script::dev
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Definition: reg_script.h:78
reg_script::size
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Definition: reg_script.h:67
reg_script::reg
uint32_t reg
Definition: reg_script.h:68
reg_script::command
uint32_t command
Definition: reg_script.h:65
reg_script::mask
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Definition: reg_script.h:69
reg_script::timeout
uint32_t timeout
Definition: reg_script.h:71
reg_script::type
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Definition: reg_script.h:66
reg_script::id
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Definition: reg_script.h:73
void
typedef void(X86APIP X86EMU_intrFuncs)(int num)